Vector Register Aliasing for Low-Latency Data Movement
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Solution Overview
Problem
Classical implementations of vector-vector moves in vector processors consume multiple clock cycles and physical registers, leading to increased power consumption and limited register renaming capabilities, especially for large vector lengths.
Innovation Solution
A method that maps multiple logical registers to a single physical register during vector-vector moves, using alias counters and a Register Alias Table (RAT) to track assignments, allowing data movement operations to complete in three clock cycles without accessing the Vector Register File (VRF).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If classical implementation of vector-vector moves is used, then data is copied from source to destination register, but multiple clock cycles and physical registers are consumed leading to increased power consumption and limited register renaming capabilities
Solution Approach 1:
The patent uses a copy of the source physical register index in the destination physical register file entry, rather than physically copying data. The destination entry stores a reference (copy of index) to the source register, allowing multiple logical registers to alias the same physical register. This eliminates actual data movement while maintaining the illusion of separate registers, resolving the contradiction between fast execution and register availability.
Solution Approach 2:
The patent introduces an intermediary mechanism (the alias counter and register indexing system) that mediates between the source and destination registers. Instead of direct data copying, the system uses index copying and alias tracking as an intermediary layer, allowing the functional unit to access data through referenced indices without actual data movement through the register file.
2Productivity
If classical implementation of vector-vector moves is used, then data movement operation is performed, but power consumption increases due to multiple VRF accesses
Solution Approach 1:
The patent copies only the register index (a small integer) rather than the actual vector data (which may contain hundreds or thousands of elements). This index copying operation in the renaming stage requires minimal energy compared to physical data movement through the VRF, while still achieving the effect of register allocation for the destination logical register.
Solution Approach 2:
The patent extracts the essential information needed for data movement (the register index) and separates it from the actual data payload. By operating on the extracted index rather than the full data, the system achieves register allocation and data movement semantics with minimal energy expenditure, avoiding unnecessary VRF accesses.
3Adaptability or versatility
If classical implementation of vector-vector moves is used, then physical registers are consumed for destination register, but register renaming capabilities are limited
Solution Approach 1:
The patent merges multiple logical register entries to point to the same physical register by storing copies of the source physical register index in destination entries. This allows multiple logical registers to alias the same physical register resource, effectively increasing the number of available logical registers beyond the physical register count and enhancing register renaming capabilities without requiring additional physical registers.
Solution Approach 2:
The patent makes each physical register capable of serving multiple logical registers simultaneously through the aliasing mechanism. A single physical register entry can be referenced by multiple logical register indices, allowing the physical register file to fulfill multiple logical register functions, thereby increasing adaptability and register renaming capacity without increasing physical register quantity.
Data Source
AI summary
The present invention discloses a computer implemented method for efficient data movement operations in vector processors comprising a number of logical registers (1), a larger number of physical registers (2), and a set of alias counters (5), wherein each alias counter (5) corresponds to a physical register (2) and stores the number of different logical registers (1) to which said physical register (2) is simultaneously assigned. The method of the invention consists of copying the first v, (vector length (4)) elements of a source vector from a source logical register (8) assigned to a source physical register (10) into a destination vector in a destination logical register (9) assigned to a destination physical register (11). This is done by assigning the source physical register (10) to the destination logical register (9), thus freeing the destination physical register (11) and by increasing in one unit the alias counter (5) associated to the source physical register (10) denoting that said source physical register (10) is assigned to more than one different logical registers (1) simultaneously.