VLIW Conditional Extension Slots for Fixed-Length Parallel Execution
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Solution Overview
Problem
In VLIW processors, conditional instruction execution techniques face challenges due to the limited opcode space for specifying multiple registers, which can lead to increased instruction length and reduced efficiency, especially when dealing with parallel functional units.
Innovation Solution
The solution involves employing two conditional execution auxiliary instructions directed at disparate subsets of the plural functional units and dividing the functional units into scalar and vector sets with separate register files, limiting simultaneous access to optimize register usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If more registers are available to control conditional execution, then conditional execution capability is improved, but the number of bits needed to specify registers increases, reducing opcode space
Solution Approach 1:
The patent segments the functional units into two disjoint sets (first set and second set) and provides separate auxiliary instructions for each set. This segmentation allows the register specification bits to be divided into two groups, each handled by a dedicated auxiliary instruction, thereby reducing the bit requirement for each group while maintaining the ability to control conditional execution for all functional units.
2Adaptability or versatility
If the instruction length is extended to accommodate more register specifications, then conditional execution capability is improved, but fixed instruction length requirement is violated
Solution Approach 1:
The patent divides the functional units into two disjoint sets and provides separate auxiliary instructions for each set. This allows the register specification to be segmented across two instructions rather than requiring a single extended instruction, thereby maintaining fixed instruction length while achieving comprehensive register control capability.
Solution Approach 2:
The patent creates two universal auxiliary instructions that can each handle conditional execution for any subset of functional units. These auxiliary instructions are multi-functional, capable of working with different functional unit sets, thereby providing flexible register specification without requiring extended instruction lengths.
3Adaptability or versatility
If multiple auxiliary instructions are provided for different functional unit sets, then conditional execution flexibility is improved, but instruction complexity increases
Solution Approach 1:
The patent designs two auxiliary instructions that are universal in nature, each capable of controlling conditional execution for different sets of functional units. These auxiliary instructions share common operational characteristics and can be used interchangeably for different functional unit sets, reducing the perceived complexity despite providing flexible control over multiple functional units.
Data Source
AI summary
In an example, a device includes registers; functional units; and an instruction decoder coupled to the registers and to the functional units. In operation, the instruction decoder receives a packet that includes instructions and a constant extension slot, the instructions including an instruction designated for execution by a specific functional unit, the instruction including a first field specifying a first register as a destination of a result of executing the instruction, a second field specifying a constant for the instruction, a third field specifying a second register as a source of an operand for the instruction, a fourth field indicating whether the constant is to be extended to generate an extended constant. In operation, the specified functional unit executes the instruction using the operand from the second register, and one of the constant from the second field or the extended constant based on a value of the fourth field.