Composite Gate Structure for BCD Circuit Fabrication
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Solution Overview
Problem
The integration of Double-Diffused Metal Oxide Semiconductor (DMOS) elements into Bipolar-CMOS-DMOS (BCD) circuits is complicated and not easily fabricated, posing challenges in designing integrated circuits for both low and high voltage ranges.
Innovation Solution
A semiconductor device structure and fabrication method that includes a substrate with a cell region and a high-voltage region, featuring a memory cell with a memory gate and selection gate, and a high-voltage transistor with a composite gate structure comprising a first and second gate structure separated by an insulating layer, where the insulating layer and spacers are derived from the same preliminary dielectric layer, facilitating easier integration and compatibility with memory cell fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional DMOS structure is used in BCD circuit, then high voltage circuit function is achieved, but fabrication complexity increases and integration difficulty arises
Solution Approach 1:
The patent applies universality by designing a composite gate structure that serves multiple functions: it provides high voltage breakdown capability through the insulating layer while maintaining compatibility with standard CMOS fabrication processes. The same basic structure can be used for both high voltage DMOS devices and standard CMOS devices, simplifying the overall fabrication process.
Solution Approach 2:
The gate structure is segmented into multiple functional layers: a conductive gate electrode, an insulating layer (such as oxide or nitride), and a dielectric layer. This segmentation allows each layer to be optimized for its specific function while being fabricated using sequential deposition processes that are already part of standard CMOS technology.
2Adaptability or versatility
If DMOS elements are integrated into BCD circuit, then both low voltage and high voltage operations are enabled, but fabrication process compatibility decreases
Solution Approach 1:
The composite gate structure is designed to be universal across different device types. The same fabrication steps—depositing conductive layers, insulating layers, and dielectric layers—can be used to create both high voltage DMOS devices and standard low voltage CMOS devices, ensuring process compatibility throughout the BCD circuit fabrication.
Solution Approach 2:
The insulating and dielectric layers are deposited in advance during the gate formation process, before subsequent doping and contact formation steps. This preliminary action ensures that the high voltage structure is already in place to guide subsequent fabrication steps, maintaining compatibility with the overall process flow.
3Reliability
If complex DMOS fabrication process is used, then high voltage transistor performance is achieved, but manufacturing organization and process integration deteriorate
Solution Approach 1:
The patent merges the high voltage DMOS fabrication process with the standard CMOS fabrication process by using the same sequence of deposition and patterning steps for both device types. The composite gate structure fabrication is combined with the memory cell fabrication process, allowing simultaneous formation of both high voltage and low voltage devices in the same process batch.
Data Source
AI summary
A semiconductor device includes a substrate, having cell region and high-voltage region. A memory cell is on the substrate within the cell region. The memory cell includes a memory gate structure and a selection gate structure on the substrate. A first spacer is sandwiched between or respectively on sidewalls of the memory cell structure and the selection gate structure. First high-voltage transistor is on the substrate within the high-voltage region. A first composite gate structure of the first high-voltage transistor includes a first gate structure on the substrate, an insulating layer with a predetermined thickness on the substrate in a -like structure or an L-like structure at cross-section, and a second gate structure on the insulating layer along the -like structure or the L-like structure. The selection gate structure and the second gate structure are originated from a same preliminary conductive layer.