Solid-State Devices TRIZ Cases

A charge trapping field effect transistor uses a conductive region to reduce fringe electric fields and prevent charge leakage in memory cells.

Bonding a resistance change device to a smooth back surface reduces wiring resistance and parasitic capacitance caused by front-side level differences.

Merging light emitting layers via phosphor conversion reduces circuit complexity and device weight while maintaining wavelength versatility.

A dielectric hardmask laterally confines conductive filaments in resistive memory elements to stabilize switching states.

Identical transistor positions and orientations within 2x2 Bayer-pattern units reduce Gb-Gr sensitivity differences, enhancing image resolution accuracy.

Microwave irradiation replaces thermal heating to reduce fabrication time and eliminate organic solvents while enhancing moisture barrier properties.

A parallel resistance region using metal oxide suppresses current variations to ensure distinct off-state levels and improve reliability.

A foldable display device integrates component areas with transmissive portions that overlap auxiliary sub-pixels to preserve light transmission.

Curved micro-mirrors redirect passthrough light back onto the photodiode to resolve light loss and crosstalk in smaller pixels.

Thin-film rectifiers and fuses integrate into a COB LED module, resolving space and cost trade-offs while ensuring reliable AC operation.

A semiconductor device uses a composite gate structure with an insulating layer to simplify high-voltage transistor fabrication.

Non-orthogonal clamp elements reduce capacitive coupling and parasitic leakage between bit lines, preventing data corruption during programming operations.

A micro LED display uses an adhesive layer to bond light-emitting structures to a wafer-level substrate with integrated control circuits.

A visible light communication apparatus integrates photoelectric conversion and light-emitting components on a single TFT substrate.

A clock multiplexer routes internal signals to latch circuits during test operations.

An expandable sheet enables precise alignment of the wavelength conversion layer, resolving uneven light color distribution in white LED manufacturing.

Segmented dies with distinct phosphors adjust spectral content via current control, resolving fixed CRI limitations in mood lighting.

Merging DQS signals from parallel inverters across stacked memory chips eliminates timing shifts caused by manufacturing deviations.

A ribbed connector strip bridges a bonding pad to a current-spreading film, enabling uniform electrical distribution across an LED.

Vertical protrusions with wall structures provide even surfaces for touch lines, resolving space constraints in high-resolution displays.

A unit picker and flipper arrange integrated circuit units on a sputtering film frame with precise clearance.

Plasma-based dry etching patterns underbump metallization layers, eliminating pattern-dependent wet chemical non-uniformities and material loss.

Ring-shaped epitaxial electrodes and condensing parts restrict light paths to prevent crosstalk between adjacent pixels.

Carbon films protect gate sidewalls during etching, resolving insufficient selectivity and preventing excessive semiconductor material consumption.

Segmented bonding positions classify chips by characteristics to improve packaging efficiency while maintaining process simplicity.

A negatively charged layer cancels induced positive charges in the contact etch stop layer to eliminate memory effects and ghost artifacts.

A light emitting diode epitaxial layer with root-mean-square roughness below 3 nm reduces surface plasmon absorption to improve light extraction.

Temporary substrate transfer eliminates bulky backlight modules, reducing display weight and thickness while maintaining high contrast.

Varying aperture ratios in opening patterns ensures uniform sidewall protection film supply, preventing pattern formation failures at the wafer edge.

A low-resistance electrode pattern overlaps gate and data metal patterns to reduce common electrode resistance.

Forming a depletion layer between the heater plug and recording layer reduces the reset current Ireset below lithography limits.

Segmented carbon nanotubes expose portions to the cathode while remaining insulated from the anode, resolving conductivity loss from polymer coverage.

Laser processing creates fracture points on a reinforcing substrate to divide optical device wafers without altering surfaces or weakening die strength.

Varying sub-pixel dimensions optimize aperture ratio in organic electroluminescence displays.

Segmented light blocking members reduce parasitic capacitance while suppressing external light reflection to improve OLED contrast ratio.

Doped glass diffusion forms extension regions in ETSOI transistors, avoiding implant damage that degrades carrier mobility and increases series resistance.

Segmented phosphor placement manages heat dissipation from inefficient red emitters while minimizing interabsorption for stable color output.

Negative fixed charge layers in deep trenches reduce dark current and white spot occurrences in highly integrated image sensors.

Internal data transfer mechanisms consolidate memory arrays without external IO lines, reducing power consumption and bandwidth usage.

An auxiliary emitter region separated by a base segment increases critical saturation current without raising reverse recovery losses.

Vertical stacking of parallel transistors sharing electrodes increases on-state current without reducing aperture ratio.

Merging determining circuits with comparing arrays reduces chip area by eliminating scattered placement and irregular shapes.

Multi-layer sidewall protection preserves NO stack integrity and trench dimensions during ONO removal, reducing epitaxial growth defects.

A parallel-path memory cell structure concentrates heating to reduce programming power and minimizes resistance drift for stable multi-bit operation.

An embossing member presses an auxiliary electrode against a cathode to reduce surface resistance and driving voltage.

A semiconductor light-emitting element uses a second electrode containing nanoscale voids to diffusely reflect light and enhance extraction.

A photodiode array uses a through-hole passing through semiconductor regions to reduce distance between adjacent elements.

Compressive stress from a capping layer counteracts tensile forces during curing to prevent substrate cracking and wire flaking.

Side connection contacts overlap isolation layers to shrink floating diffusion regions, improving conversion gain and reducing image lag.

A flexible drive circuit board bends around a support plate to create an extremely narrow bezel design.