DQS Output Circuit Timing Shift Reduction in Flash Memory

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Solution Overview

Problem

In flash memory devices with multiple stacked memory chips, timing shifts between data output from individual chips and the DQS signal can occur due to manufacturing deviations, leading to inaccurate data retrieval by the host computer.

Innovation Solution

The semiconductor memory device employs a DQS output circuit with parallel inverters for each memory chip, where the DQS signal from a subset of these inverters is combined and output through a single DQS terminal, synchronizing the data output timing across multiple memory chips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple memory chips are stacked to increase storage capacity and data bit width, then the storage capacity and data throughput are improved, but timing shifts between data output from individual chips and the DQS signal occur due to manufacturing deviations

Engineering Contradiction:

Improvestorage capacityVSAvoidtiming alignment

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent combines DQS signals from multiple memory chips into a single shared DQS terminal. Instead of maintaining separate DQS terminals for each chip, the invention merges the DQS output circuits of multiple chips to drive a common DQS signal line, thereby unifying the timing reference for data output across all stacked chips and eliminating timing shifts caused by manufacturing variations.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared DQS terminal serves as a universal timing reference for data output from multiple different memory chips. The single DQS terminal universally defines the timing for data output across all chips in the stack, allowing the system to maintain synchronized data retrieval despite variations in individual chip characteristics.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Device complexity

If a single DQS terminal is used for multiple memory chips, then the device complexity is reduced, but the timing accuracy between data output and DQS signal deteriorates due to signal distribution delays

Engineering Contradiction:

ImproveDQS terminal quantityVSAvoiddata timing accuracy

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The patent merges the DQS output circuits of multiple memory chips to drive a single shared DQS terminal. By combining the DQS signal generation capabilities of multiple chips into one unified signal source, the invention reduces the number of DQS terminals while maintaining timing accuracy through the coordinated operation of multiple DQS output circuits feeding the same terminal.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS10636497B2Semiconductor memory device, manufacturing method thereof and output method of data strobe signal

Publication Date: 2020.04.28 WINBOND ELECTRONICS CORP

AI summary

A semiconductor memory device suppressing a shift between data output from a plurality of memory chips and a DQS signal. A flash memory device of the disclosure includes memory chips, a plurality of IO terminals capable of inputting and outputting data, and a DQS terminal. Each of the memory chips includes an output circuit used to output data and a DQS output circuit. The DQS output circuit is used to output the DQS signal for defining a timing of the data output from the output circuit. The DQS signal output from each of the DQS output circuits of the memory chips is supplied to the DQS terminal.