Non-orthogonal clamp elements for phase change memory arrays
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Solution Overview
Problem
High memory density in semiconductor memories leads to challenges in fabricating clamp elements to control coupling capacitances and prevent data corruption due to spurious currents between bit lines during programming operations.
Innovation Solution
The implementation of non-orthogonal wall self-heating type cell structures with chalcogenic materials and switches, arranged adjacent to bit lines and voltage control word lines, to control voltage and prevent unwanted programming of unaddressed cells by using clamp elements that include a cap, a chalcogenic material, and a switch, which are self-heating and phase change materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory density is increased to achieve higher storage capabilities and operating frequencies, then storage capacity and speed are improved, but coupling capacitances between bit lines increase causing spurious currents and data corruption
Solution Approach 1:
Clamp elements are introduced as intermediary components connected to bit lines to control and limit voltage levels. These clamp elements act as mediators that prevent spurious currents from propagating between adjacent bit lines, thereby eliminating data corruption while preserving the high-density memory architecture.
Solution Approach 2:
The clamp elements dynamically adjust voltage parameters on bit lines by clamping excessive voltage excursions. This parameter control prevents the coupling capacitance from generating harmful spurious currents, allowing high-density memory operation without data corruption.
2Reliability
If clamp elements are added to control coupling capacitance and prevent spurious currents, then data integrity is improved, but device complexity and fabrication difficulty increase
Solution Approach 1:
The clamp element is merged with the existing memory cell structure, sharing common components such as transistors and capacitors. This integration approach reduces overall device complexity by eliminating redundant structures while maintaining the voltage control function necessary for data integrity.
Solution Approach 2:
The clamp element is designed to perform multiple functions: voltage clamping to prevent spurious currents, data storage capability, and participation in programming operations. This multi-functionality reduces the need for separate dedicated components, thereby simplifying the overall memory structure.
3Reliability
If clamp elements are added to control voltage and prevent data corruption, then reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The clamp element is designed with homogeneous structural characteristics that match the existing memory cell geometry and fabrication processes. By using the same material layers, transistor designs, and capacitor structures as the memory cells, the clamp element can be manufactured with the same precision requirements, avoiding the need for additional manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces capacitive coupling and parasitic leakage between bit lines, preventing data corruption and allowing for the formation of clamp elements in high-density memory arrays, thereby enhancing programming accuracy and efficiency.
Implementation Method 1
the self-heating type cell structure includes a cap, a chalcogenic material, and a switch, and wherein the chalcogenic material is both self-heating and a phase change material
Implementation Method 2
the self-heating type cell structure includes a cap, a chalcogenic material, and a switch, and wherein the chalcogenic material is both self-heating and a phase change material
Data Source
AI summary
Clamp elements, memories, apparatuses, and methods for forming the same are disclosed herein. An example memory may include an array of memory cells and a plurality of clamp elements. A clamp element of the plurality of clamp elements may include a cell structure formed non-orthogonally relative to at least one of a bit line or a word line of the array of memory cells and may be configured to control a voltage of a respective bit line.