Charge-Trapping Memory Device with Conductive Region
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Charge leakage in charge-trapping (CT) flash memory cells leads to degraded performance, causing program saturation and unwanted charge trapping in spacers or insulating regions, which affects the reliability and efficiency of memory devices.
Innovation Solution
The implementation of a charge trapping field effect transistor (FET) with a semiconductor substrate, doped regions, and a gate structure that includes a charge trapping dielectric region and a conductive region, where the charge trapping heterogeneous dielectric region has increased silicon content for enhanced conductive properties, and the conductive region reduces fringe electric fields to prevent charge leakage and unwanted trapping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional charge-trapping flash memory cell uses two oxide layers for isolation, then the CT layer is electrically isolated, but charge leakage occurs leading to degraded performance
Solution Approach 1:
The patent uses a composite charge trapping structure consisting of a charge trapping dielectric layer (e.g., silicon-rich nitride) combined with a conductive layer (e.g., polysilicon or metal). This composite structure provides both charge trapping capability and conductive properties to prevent charge leakage, resolving the contradiction between isolation and charge retention.
Solution Approach 2:
The patent modifies the electrical properties of the charge trapping layer by adjusting its composition (increased silicon content in silicon-rich nitride) and adding a conductive layer, changing the parameter of electrical conductivity from insulating to conductive, thereby preventing charge leakage while maintaining trapping functionality.
2Reliability
If the CT layer is surrounded by dielectric material for isolation, then electrical isolation is achieved, but fringe electric fields cause unwanted charge trapping in spacers or insulating regions
Solution Approach 1:
The conductive layer acts as an intermediary between the charge trapping dielectric and the surrounding environment. It provides a controlled path for electric field distribution, preventing fringe fields from extending into spacers and insulating regions, thereby eliminating unwanted charge trapping in those areas.
3Quantity of substance
If the charge trapping dielectric has standard composition, then it provides basic charge trapping, but program saturation occurs due to charge leakage
Solution Approach 1:
The patent creates a composite structure where the charge trapping dielectric (providing charge storage capacity) is combined with a conductive layer (preventing charge leakage). This composite approach maintains full charge trapping capacity while preventing program saturation through the conductive pathway that eliminates leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances memory cell performance by preventing charge leakage and program saturation, providing more reliable and improved memory cell performance compared to current CT memory devices.
Implementation Method 1
The gate structure includes a charge trapping dielectric region and a charge trapping conductive region in contact with the charge trapping dielectric region
Implementation Method 2
the conductive region reduces fringe electric fields to prevent charge leakage and unwanted trapping
Data Source
AI summary
A structure and method for providing improved and reliable charge trapping memory device are disclosed herein. A charge trapping field effect transistor (FET) comprising a semiconductor substrate, a doped region in the semiconductor substrate, and a gate structure on the semiconductor substrate and a method of fabricating the same are also discussed. The doped region comprises a first lateral dimension along a first direction. The gate structure comprises a charge trapping dielectric region and a charge trapping conductive region in contact with the charge trapping dielectric region.