Parallel-Path Phase Change Memory Cell Structure
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Solution Overview
Problem
Phase change memory (PCM) technologies face challenges in reducing programming power and peak current, minimizing resistance drift, and ensuring data retention for multi-bit operation, as existing methods either rely on post-processing techniques or create small amorphous regions that are sensitive to trap relaxation and recrystallization.
Innovation Solution
A parallel-path memory cell structure is developed with two electrodes contacting the same side of a germanium-antimony-tellurium (GST) layer, featuring a sublithographic trench and insulator layer configuration that concentrates heating and reduces the need for a top electrode, allowing for efficient energy use and minimizing resistance drift through controlled amorphous and crystalline region sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a conventional PCM cell structure with series electrical path is used, then the device can store data by altering material phase, but the programming power and peak current are excessive
Solution Approach 1:
The patent divides the electrical path into two parallel segments instead of using a single series path. The first electrical path goes through the first electrode, phase change material, and second electrode, while the second electrical path provides an alternative route through doped semiconductor regions. This segmentation allows current to be distributed across multiple paths, reducing peak current and programming power requirements.
Solution Approach 2:
The patent transitions from a one-dimensional series electrical path to a two-dimensional parallel path configuration. By adding the second electrical path that runs parallel to the first path through different material layers (doped semiconductor regions instead of phase change material), the device creates multiple current flow dimensions, enabling reduced power operation while maintaining data storage functionality.
2Adaptability or versatility
If small amorphous regions are created for multi-bit operation, then data storage capacity increases, but resistance drift increases due to sensitivity to trap relaxation and recrystallization
Solution Approach 1:
The patent creates distinct local regions with different properties: a first amorphous region in the first electrical path and a second amorphous region in the second electrical path. Each region can be independently controlled and has specific characteristics optimized for its function. The doped semiconductor regions in the second path provide stable resistance characteristics that reduce overall resistance drift while maintaining multi-bit storage capability.
Solution Approach 2:
The patent uses a composite structure combining phase change material with doped semiconductor materials. The doped semiconductor regions (n-type or p-type) in the second electrical path provide stable electrical characteristics that compensate for the instability of small amorphous regions. This composite approach allows the device to achieve multi-bit operation with improved data retention by leveraging the complementary properties of different materials.
3Loss of energy
If a top electrode is used in conventional PCM cells, then electrical contact is achieved, but heat dissipation increases reducing energy efficiency
Solution Approach 1:
The patent removes the conventional top electrode structure from the phase change material. Instead of using a separate top electrode to make electrical contact, the device uses the second electrode that is already in contact with the phase change material and extends to form the electrical connection. This extraction of the redundant top electrode reduces heat dissipation to the substrate and improves energy efficiency while maintaining necessary electrical contact through the streamlined electrode configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces programming power and peak current, minimizes resistance drift, and enhances data retention by maintaining resistance stability across varying amorphous and crystalline regions, enabling efficient multi-bit operation.
Implementation Method 1
Phase change materials can be manipulated into two or more different phases or states, with each phase representing a different data value. Generally, each phase exhibits different electrical properties (or different resistance values). The amorphous and crystalline (or polycrystalline) phases are typically two phases used for binary data storage (1's and 0's) since they have detectable differences in electrical resistance.
Implementation Method 2
A current passed through the phase change material creates heat and causes the phase change material to melt.
Implementation Method 3
Melting and abruptly cooling the phase change material quenches the phase change material into the amorphous state.
Implementation Method 4
Melting and gradually cooling down the phase change material allows time for the phase change material to form the crystalline state.
Data Source
AI summary
A method of manufacturing a phase change memory cell on a substrate. The method includes: etching a first trench in the substrate; depositing a first conductor layer in the first trench; depositing a first insulator layer over the first conductor layer in the first trench; etching a second trench in the substrate at an angle to the first trench; depositing a second insulator layer in the second trench; depositing a second conductor layer over the second insulator layer in the second trench; and depositing phase change material. The deposited phase change material is in contact with the first conductor layer and the second conductor layer.