On-Die Data Transfer in Memory Devices

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Solution Overview

Problem

Conventional memory devices require external data lines for data consolidation, reconsolidation, and manipulation, leading to power-intensive and bandwidth-consuming processes due to the need to read and rewrite data across the memory array, which can result in data fragmentation and loss.

Innovation Solution

The implementation of memory devices with internal data transfer capabilities, utilizing local and global caches, data read/write lines, and tracking mechanisms to move data within the device without relying on external IO or DQ data lines, allowing for flexible consolidation, reconsolidation, and rearrangement of data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If external data lines are used for data consolidation and manipulation, then data can be transferred between memory locations, but power consumption increases and IO bandwidth is consumed

Engineering Contradiction:
Improvepower consumptionVSAvoiddata transfer capability
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent extracts the data transfer function from external IO paths and relocates it to internal device resources. By using internal caches and on-die transfer mechanisms, the system removes the need for external data line transactions for consolidation operations, thereby reducing power consumption and IO bandwidth usage while maintaining data transfer capability

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces internal caches as intermediary storage structures between the memory array and external IO interfaces. These caches serve as mediators that enable data consolidation and manipulation operations to occur internally without requiring external data line transactions, thus resolving the contradiction between transfer capability and power/bandwidth consumption

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If data is read and rewritten across the memory array using external lines, then data consolidation can be performed, but IO bandwidth is consumed and data fragmentation may occur

Engineering Contradiction:
Improvedata consolidation efficiencyVSAvoiddata fragmentation
Core Design Contradiction:
ProductivityVSLoss of information

Solution Approach 1:

The patent segments the memory system into distinct functional regions including memory arrays, internal caches, and control logic. This segmentation allows data consolidation operations to be performed within specific internal regions without affecting the entire memory array, thereby preventing data fragmentation while maintaining consolidation productivity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Internal caches act as intermediary structures that facilitate data consolidation without requiring external read-rewrite cycles. By transferring data between internal cache regions rather than through external IO lines, the system achieves efficient consolidation while preventing data fragmentation that would occur with external line transactions

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of energy

If internal data transfer mechanisms are implemented, then power consumption and IO bandwidth usage are reduced, but device complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidinternal data transfer capability
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent implements multi-functional internal caches that serve multiple purposes: they act as temporary storage during read/write operations, enable data consolidation without external IO, provide buffering for timing synchronization, and support on-die data transfer. This universality reduces the need for separate dedicated structures, thereby limiting the increase in device complexity while achieving energy savings

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11024367B2Memory with on-die data transfer
Publication Date: 2021.06.01 MICRON TECHNOLOGY INC
  • US11024367B2 patent drawing
  • US11024367B2 patent drawing
  • US11024367B2 patent drawing

AI summary

Memory devices and systems with on-die data transfer capability, and associated methods, are disclosed herein. In one embodiment, a memory device includes an array of memory cells and a plurality of input/output lines operably connecting the array to data pads of the device. In some embodiments, the memory device can further include a global cache and/or a local cache. The memory device can be configured to internally transfer data stored at a first location in the array to a second location in the array without outputting the data from the memory device. To transfer the data, the memory device can copy data on one row of memory cells to another row of memory cells, directly write data to the second location from the first location using data read/write lines of the input/output lines, and/or read the data into and out of the global cache and/or the local cache.