Protective Layer Structure for 3D NAND Flash Memory Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for forming 3D NAND flash memory devices face challenges in removing the oxide-nitride-oxide (ONO) structure without damaging the underlying nitride-oxide (NO) stack structure, leading to performance degradation due to similar film properties and subsequent sidewall epitaxial growth defects.
Innovation Solution
A method involving the formation of a protective layer structure, including multiple layers such as silicon nitride, silicon oxide, and titanium nitride, on the sidewall of the gate-line trench to protect the NO stack structure during the removal of the ONO structure, using these layers as etch masks to selectively remove the sacrificial layers and prevent damage to the NO stack and gate-line capping layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the ONO structure is removed using conventional etching methods, then the sacrificial layer can be exposed for subsequent epitaxial growth, but the NO stack structure is damaged due to similar film properties causing performance degradation
Solution Approach 1:
The patent segments the protective structure into multiple distinct layers (first protective layer, second protective layer, third protective layer) with different materials and etching resistances. This segmentation allows selective removal of the ONO structure while preserving the NO stack structure, as each layer can be etched at different rates or with different etchants.
Solution Approach 2:
The patent introduces protective layers as intermediary structures between the etching process and the NO stack structure. These intermediary layers act as barriers that prevent direct contact between the etchant and the sensitive NO stack, thereby preventing damage while still allowing the ONO structure to be removed.
2Ease of manufacture
If sidewall selective epitaxial growth is performed without protective layers, then the fabrication process is simpler, but defects occur during epitaxial growth due to exposure of the NO stack structure
Solution Approach 1:
The patent performs preliminary actions by forming multiple protective layers before the epitaxial growth process. These layers are prepared in advance to ensure that when epitaxial growth occurs, the NO stack structure is already protected, preventing defects from forming during the growth process.
Solution Approach 2:
The protective layers serve as beforehand cushioning structures that absorb or mitigate potential damage during the epitaxial growth process. By placing these protective barriers in advance, the patent prevents defects from occurring rather than correcting them afterward.
3Device complexity
If conventional single-layer protective structure is used, then the process is simpler, but insufficient protection is provided against etching damage to the NO stack structure
Solution Approach 1:
The patent uses composite materials by combining multiple protective layers made of different materials (first protective layer, second protective layer, third protective layer). Each material is selected for its specific properties, creating a composite protective structure that provides superior protection compared to a single-layer structure.
Solution Approach 2:
The patent implements a nested structure where the first protective layer, second protective layer, and third protective layer are arranged in concentric or sequential layers. This nested arrangement allows each layer to provide protection at different levels, with the innermost layers providing direct protection to the NO stack structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents damage to the NO stack structure and gate-line capping layer, maintains the dimensions of the gate-line trench, and reduces defects during sidewall selective epitaxial growth, thereby enhancing the performance and reliability of the 3D NAND flash memory devices.
Implementation Method 1
forming at least one protective layer on the sidewalls of the gate-line trench; removing the first sacrificial layer to expose a portion of each of the plurality of channels and the surfaces of the base substrate, using the at least one protective layer as an etch mask
Implementation Method 2
forming an epitaxial layer on the exposed surfaces of the base substrate and the plurality of channels
Data Source
AI summary
A method for forming a memory device includes providing an initial semiconductor structure, including a base substrate; a first sacrificial layer formed on the base substrate; a stack structure, disposed on the first sacrificial layer; a plurality of channels, formed through the stack structure and the first sacrificial layer; and a gate-line trench, formed through the stack structure and exposing the first sacrificial layer. The method also includes forming at least one protective layer on the sidewalls of the gate-line trench; removing the first sacrificial layer to expose a portion of each of the plurality of channels and the surfaces of the base substrate, using the at least one protective layer as an etch mask; and forming an epitaxial layer on the exposed surfaces of the base substrate and the plurality of channels.