Semiconductor Wafer Edge Pattern Failure Prevention
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Solution Overview
Problem
Miniaturization of semiconductor patterns leads to pattern formation failures at the edge of semiconductor wafers due to nonuniform sidewall protection film supply and unstable resist thickness, resulting in pattern resolution failures and foreign objects.
Innovation Solution
A semiconductor device with a main chip region and a smaller sub-chip region adjacent to it, both having identical design patterns, is manufactured using a method where the photosensitive material is exposed to light patterns and developed to prevent pattern failures by ensuring consistent sidewall protection and stable resist application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a blank region is provided at the edge of a wafer, then chip arrangement is simplified, but sidewall protection film supply becomes nonuniform causing pattern formation failure
Solution Approach 1:
The invention applies different aperture ratios in different regions of the opening pattern. Specifically, the aperture ratio is set to 25% or more in regions adjacent to blank regions and 10% or more in other regions. This local variation in pattern density ensures uniform sidewall protection film supply across the entire wafer surface, preventing pattern formation failures at wafer edges while maintaining ease of chip arrangement.
2Manufacturing precision
If opening pattern is arranged on the entire surface of a wafer, then sidewall protection film supply is improved, but beveled region causes unstable resist thickness and patterning failure
Solution Approach 1:
The invention addresses the beveled region problem by applying local quality principles with different aperture ratios. In beveled regions where resist thickness is unstable, the opening pattern is designed with higher aperture ratios (25% or more) to compensate for the unstable conditions. This ensures sufficient sidewall protection film supply in problematic regions while maintaining overall patterning reliability across the wafer surface.
3Productivity
If miniaturized pattern is used, then chip performance is improved, but pattern collapse and foreign objects occur due to insufficient sidewall protection film
Solution Approach 1:
The invention uses parameter changes by varying the aperture ratio of the opening pattern based on local conditions. For miniaturized patterns that are prone to collapse, the aperture ratio is increased to 25% or more in critical regions. This parameter adjustment ensures adequate sidewall protection film supply to support the fine patterns, preventing pattern collapse and foreign object formation while maintaining the performance benefits of miniaturization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents pattern formation failures at the wafer edge by ensuring consistent sidewall protection and stable resist application, achieving high accuracy and preventing pattern collapse and foreign objects.
Implementation Method 1
a photosensitive material is formed on a main surface of a semiconductor wafer. a first chip formation region of the photosensitive material is exposed to light of a first pattern. a second chip formation region of the photosensitive material adjacent to and smaller than the first chip formation region is exposed to light of a second pattern
Data Source
AI summary
A semiconductor wafer has a main surface. A main chip region is formed on the main surface. A sub-chip region is smaller in area than the main chip region, and positioned on an edge side of the semiconductor wafer relative to the main chip region. The sub-chip region is identical to the main chip region in design pattern. Accordingly, a semiconductor device in which occurrence of a pattern failure at the edge of the wafer can be prevented when chips are arranged in the surface of the semiconductor wafer and a method of manufacturing the same can be obtained.


