Semiconductor Circuit Block Layout for Chip Area Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor device layouts with redundant circuits result in inefficient use of space due to scattered arrangements of determining circuits, leading to increased chip area and higher manufacturing costs.
Innovation Solution
A layout where unit circuits, processing circuits, and common circuits are arranged in a structured manner, allowing for adjacent placement within the same or multiple circuit blocks, reducing waste and enabling a more compact design by forming rectangular or L-shaped blocks that can be repeatedly arranged without gaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If determining circuits are arranged in a scattered manner along the direction of arranging comparing circuits, then each determining circuit can be allocated to corresponding comparing circuits, but the shape of the layout becomes irregular and chip area increases
Solution Approach 1:
The patent merges the determining circuit with the comparing circuit array by arranging the determining circuit adjacent to the comparing circuits in the same layout block. This integration allows the determining circuit to serve multiple comparing circuits simultaneously, eliminating the need for scattered placement and reducing overall chip area while maintaining proper circuit allocation.
Solution Approach 2:
The determining circuit is designed to handle comparison results from multiple comparing circuits through a unified structure. By positioning it adjacent to the comparing circuit array, a single determining circuit can process signals from multiple comparing circuits, reducing the total number of determining circuits needed and minimizing layout irregularities.
2Ease of manufacture
If comparing circuits are arranged with smaller pitch than fuse elements, then space is provided for common signal lines, but the layout becomes less efficient and chip area increases
Solution Approach 1:
The patent combines the arranging of comparing circuits and common signal lines into a unified layout structure. By positioning common signal lines in the spaces naturally formed by the comparing circuit array, the design achieves efficient space utilization without requiring additional area, as the signal lines occupy otherwise unused gaps in the compact comparing circuit pitch arrangement.
3Area of stationary object
If circuit blocks are arranged with regular shapes, then layout efficiency is improved and chip area is reduced, but flexibility in accommodating scattered determining circuits is limited
Solution Approach 1:
The patent segments the semiconductor device into multiple identical circuit blocks, each containing fuse elements, comparing circuits, and a determining circuit arranged in a standardized pattern. This segmentation allows regular-shaped blocks to be tiled across the chip, achieving high layout efficiency and reduced area while maintaining flexibility through repetition of the modular unit.
Solution Approach 2:
The patent transitions from scattered two-dimensional placement of determining circuits to a structured grid-based arrangement where determining circuits are positioned at regular intervals adjacent to comparing circuit arrays. This dimensional organization transforms the layout into a repeating pattern that can be efficiently packed, reducing chip area while providing systematic flexibility for scaling.
Data Source
AI summary
To include a plurality of circuit blocks each including a plurality of nonvolatile memory elements arranged in the X direction, a plurality of comparing circuits that are respectively allocated to the nonvolatile memory elements, and a determining circuit that is commonly allocated to the comparing circuits. The nonvolatile memory elements included in a predetermined circuit block among the circuit blocks are arranged in a first area. The comparing circuits and the determining circuit included in the predetermined circuit block are arranged side by side in the X direction in a second area that is located in the Y direction with respect to the first area. With this arrangement, because the circuit block becomes a shaped block, even when a plurality of circuit blocks are repeatedly arranged, it is possible to realize a further reduction of the chip area.