Clock Multiplexer for HBM Test Mode
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Solution Overview
Problem
The testing of AC characteristics in High Bandwidth Memory (HBM) devices is challenging due to the small size of external terminals on the interface chip, making it difficult to probe and adjust multiple internal clocks, which increases test time exponentially as each clock's timing needs to be correctly set.
Innovation Solution
The implementation of a test mode that utilizes internal clocks, specifically providing the WDQS clock to the latch circuits instead of the WCLK clock, reduces the number of clocks that need to be adjusted during testing, allowing for faster identification of suitable clock timing by focusing on fewer clock adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple internal clocks are used during test operations, then the AC characteristics testing can be performed, but the test time increases exponentially due to the need to adjust each clock's timing
Solution Approach 1:
The patent extracts the clock adjustment problem by providing a single internal clock signal to multiple data paths instead of using separate clocks for each path. This reduces the number of clocks that need to be adjusted from multiple to just one, thereby dramatically reducing test time while maintaining testing accuracy
Solution Approach 2:
The patent merges multiple clock functions into a single internal clock signal that is distributed to multiple data paths. By combining the clocking function into one unified source, the system eliminates the need to independently adjust multiple clocks, thus reducing test time exponentially while still enabling comprehensive AC characteristics testing
2Area of stationary object
If the external terminal size is reduced on the interface chip, then the device integration is improved, but the probing difficulty increases
Solution Approach 1:
The patent introduces an intermediary approach by using internal clocks that can be accessed and adjusted through existing test interfaces without requiring direct probing of the small external terminals. The internal clocks serve as mediators that allow testing to proceed without the need to physically probe the reduced-size external terminals
Data Source
AI summary
Apparatuses and methods for providing clocks to data paths are disclosed. An example apparatus includes a first circuit in a data path, a second circuit in the data path, and a multiplexer. The first circuit is configured to provide data based on a first clock and the second circuit is configured to receive the data and provide the data based on a second clock. The multiplexer is configured to provide a third clock as the second clock for some test operations and further configured to provide the first clock as the second clock for other test operations. A timing of the first clock is adjusted for the first circuit during the test operations.