Bandgap Engineered SONOS Memory Cell for High-Speed Erase
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Solution Overview
Problem
Traditional flash memory technologies face challenges in increasing density due to cell-to-cell interference in floating gate memory cells and poor endurance and charge retention in charge trapping memory cells, especially with thin tunneling dielectric layers, which limits high-speed erase and program operations.
Innovation Solution
The implementation of a 2T NOR architecture using bandgap engineered SONOS (BE-SONOS) memory cells with a dielectric stack that includes a tunneling dielectric layer blocking charge tunneling at low electric fields, allowing for efficient programming and erasing while maintaining high endurance and reliability, and enabling high-speed read operations at low voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the tunneling dielectric layer is made thin to achieve high-speed erase operation, then erase speed is improved, but endurance and charge retention characteristics deteriorate
Solution Approach 1:
The patent employs a composite dielectric stack consisting of multiple layers including silicon oxide, silicon nitride, and silicon oxynitride. This composite structure enables the tunneling dielectric to achieve both thin physical thickness (for high-speed erase) and sufficient effective thickness (for reliability) by combining materials with different dielectric properties and charge trapping characteristics.
Solution Approach 2:
The patent changes the effective dielectric thickness parameter while maintaining or reducing the physical thickness. By using high-k dielectric materials and engineered dielectric stacks, the effective tunneling barrier is increased without proportionally increasing the physical layer thickness, thereby achieving both fast erase speed and good charge retention.
2Reliability
If the tunneling dielectric layer is made thick to improve endurance and charge retention, then reliability is improved, but erase speed deteriorates
Solution Approach 1:
The composite dielectric stack with multiple functional layers (tunneling oxide, charge trapping nitride, blocking oxide) allows each layer to be optimized independently. The tunneling oxide can be kept thin for fast erase, while the overall stack provides sufficient barrier thickness for reliability, resolving the speed-reliability tradeoff.
Solution Approach 2:
The charge trapping layer acts as an intermediary between the thin tunneling dielectric and the blocking dielectric. It absorbs excess electric field stress during erase operations, protecting the thin tunneling layer from breakdown while enabling fast charge injection, thus mediating between speed and reliability requirements.
3Quantity of substance
If floating gate memory cells are placed close together to increase density, then storage density is improved, but cell-to-cell interference increases
Solution Approach 1:
The patent extracts the charge storage function from the continuous floating gate structure and relocates it to discrete charge trapping sites within the dielectric stack. This spatial separation of charge storage locations reduces capacitive coupling between adjacent cells, eliminating the main source of cell-to-cell interference while maintaining high density.
Solution Approach 2:
The charge trapping layer provides distributed, localized charge storage sites throughout the dielectric volume rather than requiring continuous floating gates. This porous-like distribution of trapping centers allows for reduced cell spacing without increasing interference, as each cell's charge is confined to specific trapping sites within its own dielectric stack.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The BE-SONOS structure enables high-speed read operations, reduces power consumption, and allows for dense memory cell layouts with improved charge retention and endurance, supporting multiple bits per cell without significant interference or leakage.
Implementation Method 1
The bandgap engineered, tunneling dielectric layer includes a combination of materials arranged to establish a relatively low valence band energy level near said one of the gate and the channel surface
Implementation Method 2
The bandgap engineered, tunneling dielectric layer includes a combination of materials arranged to establish a relatively low valence band energy level near said one of the gate and the channel surface, and an increase in valence band energy level at a first distance from said one of the gate and the channel surface
Data Source
AI summary
A 2T cell NOR architecture based on the use of BE-SONOS for embedded memory includes memory cells having respective access transistors having access gates and memory transistors having memory gates arranged in series between the corresponding bit lines and one of the plural reference lines. A memory transistor in a memory cell comprises a semiconductor body including a channel having a channel surface and a charge storing dielectric stack between the memory gate and the channel surface. The dielectric stack comprises a bandgap engineered, tunneling dielectric layer contacting one of the gate (for gate injection tunneling) and the channel surface (for channel injection tunneling). The dielectric stack of the memory cell also includes a charge trapping dielectric layer on the tunneling dielectric layer and a blocking dielectric layer.