Below-Gate-Stack Source/Drain Contacts for Local Interconnect Accuracy
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Solution Overview
Problem
As semiconductor process technology scales down, process variations become increasingly challenging in manufacturing integrated circuits, particularly in forming gate vias and ensuring accurate electrical connections in field effect transistors, leading to complexity in IC design and manufacturing.
Innovation Solution
The semiconductor structure incorporates gate structures and vias arranged over active and non-active regions, with spacers and interconnects to facilitate electrical coupling, and a method for determining the placement of local interconnects based on specific guidelines to optimize connectivity and reduce complexity, allowing for efficient design and manufacturing of integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of interconnected devices per chip area is increased, then the productivity and integration density are improved, but the manufacturing precision and process control become more difficult
Solution Approach 1:
The patent divides the gate structure formation into multiple stages: first forming mandrels in the active region, then forming gate structures in both active and non-active regions, and finally selectively removing portions. This segmentation allows complex high-density integration to be achieved through manageable sequential steps, maintaining manufacturing precision despite increased device density.
Solution Approach 2:
The patent performs preliminary actions by forming mandrels and spacers before final gate structure completion. The mandrels are formed first to define future gate locations, then spacers are formed to protect certain regions. These preliminary structures guide subsequent processing steps, ensuring precise placement even as device density increases.
2Productivity
If the smallest component size is decreased, then the integration density is improved, but the manufacturing precision and process variations increase
Solution Approach 1:
The patent applies different structures and materials to different regions: mandrels are formed only in active regions while gate structures are formed in both active and non-active regions. Spacers are selectively placed to protect specific areas. This local differentiation allows precise control of component dimensions in high-density configurations by tailoring the structure to local requirements.
Solution Approach 2:
The patent employs nested structures where spacers surround mandrels, and gate structures are formed around the spacer-protected regions. This nesting provides self-alignment and dimensional control, ensuring that even as component sizes decrease, the relative positions and dimensions remain precisely controlled through the concentric relationship between nested elements.
3Reliability
If gate vias and electrical connections are formed with higher precision, then the reliability is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent inverts the conventional approach by first forming gate structures and then forming source/drain regions around them, rather than forming source/drain first and then gates. This inversion simplifies the formation of highly precise gate vias and electrical connections, as the gate structures serve as templates that automatically define the required connection locations, reducing processing complexity while maintaining reliability.
Data Source
AI summary
A method is provided, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.