Bent Backside Word Lines for Dense 3D Memory Routing
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Solution Overview
Problem
As feature sizes of planar memory cells approach their limits, traditional fabrication techniques become challenging and costly, leading to density limitations in memory devices, and scaling 3D memory architecture to increase density complicates interconnect routing and reduces core array area.
Innovation Solution
The implementation of 3D memory devices with bent backside word lines, where conductive and dielectric layers extend vertically through the memory stack on both sides of the substrate, allowing for increased routing flexibility, reduced interconnect density, and improved electrical performance by forming memory cells on both sides of the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but fabrication complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture by stacking multiple conductive and dielectric layers vertically. This dimensional change allows continued scaling and density improvement without the fabrication complexity penalties associated with further planar scaling, as the vertical stacking can be achieved through established deposition and etching processes.
Solution Approach 2:
The memory structure is segmented into multiple discrete layers - alternating conductive layers (word lines, bit lines) and dielectric layers - that are stacked vertically. This segmentation allows each layer to be formed using standard thin-film deposition techniques, avoiding the need for complex new fabrication processes while achieving high density through vertical integration.
2Quantity of substance
If 3D memory architecture is scaled to increase density, then memory density is improved, but interconnect routing complexity increases
Solution Approach 1:
The patent resolves interconnect routing complexity by utilizing the vertical dimension for interconnect formation. Word lines and bit lines are formed as separate conductive layers at different vertical levels, allowing straightforward routing without the complex lateral routing required in planar architectures. The vertical stacking naturally provides the interconnect hierarchy needed for 3D memory operation.
Solution Approach 2:
The patent employs bent word lines that extend from the front surface, curve through the vertical thickness of the memory stack, and emerge at the back surface. This curved geometry allows word lines to traverse the 3D structure efficiently, connecting to memory cells throughout the stack while maintaining manageable routing complexity compared to straight vertical or lateral connections.
3Quantity of substance
If 3D memory architecture is scaled to increase density, then memory density is improved, but core array area is reduced
Solution Approach 1:
The patent increases memory density by exploiting the vertical dimension through multi-layer stacking, rather than compressing the core array area in the lateral plane. The alternating conductive and dielectric layers extend vertically through the memory stack, enabling high density while preserving lateral dimensions for the core array. This vertical scaling approach decouples density improvement from core array area reduction.
Data Source
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Figure 1B
Figure 2A~2B
AI summary
A three-dimensional (3D) memory device having bent backside word lines is disclosed. The 3D memory device includes a substrate (102), a semiconductor layer (104) above and extending laterally beyond at least one edge (114, 116) of the substrate (102), a plurality of interleaved conductive layers (110) and dielectric layers (112) above a front side of the semiconductor layer (104) and extending below a back side of the semiconductor layer (104), and a plurality of memory strings (130, 140) each extending vertically through the interleaved conductive layers (110) and dielectric layers (112) and in contact with the semiconductor layer (104).