BEOL Twin-Channel CMOS Inverter for Short-Channel Mitigation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a need for semiconductor devices that can be integrated in the back-end-of-line (BEOL) process without damaging previously fabricated front-end-of-line (FEOL) and middle end-of-line (MEOL) devices, while allowing for further reductions in size and mitigating short-channel effects.
Innovation Solution
The development of a CMOS inverter with twin channels and a single gate electrode, formed using metal-oxide semiconductor layers in a BEOL process, which includes a vertically stacked configuration of conductivity-type semiconductor layers and gate dielectric layers, allowing for longer channel lengths without increased device size, and incorporating other BEOL components like capacitors and resistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional transistors are used to reduce minimum feature size for higher integration density, then more components can be integrated into a given area, but the fabrication process damages previously fabricated FEOL and MEOL devices
Solution Approach 1:
The fabrication process is segmented into distinct stages: FEOL processes complete the first transistor layer, then BEOL processes fabricate the oxide semiconductor transistor layer at lower temperatures. This segmentation allows each stage to operate under optimal conditions without damaging previously fabricated structures, resolving the contradiction between integration density improvement and device damage prevention.
Solution Approach 2:
The patent changes the temperature parameter for the BEOL fabrication process, using lower temperatures suitable for oxide semiconductor materials. This parameter change enables the formation of additional transistor layers without thermally damaging the previously fabricated FEOL and MEOL devices, thereby increasing integration density while preventing device damage.
2Productivity
If feature size is reduced to increase integration density, then more components fit in a given area, but short-channel effects become more severe
Solution Approach 1:
The patent transitions from planar transistor structures to vertically stacked three-dimensional structures. By stacking multiple oxide semiconductor transistor layers vertically, the design achieves higher integration density in the vertical dimension while maintaining larger horizontal feature sizes, thereby reducing short-channel effects while increasing productivity.
3Reliability
If vertically stacked configuration is used to achieve longer channel lengths, then short-channel effects are mitigated, but device complexity increases
Solution Approach 1:
The patent merges multiple transistor functions into a single vertically stacked structure where multiple oxide semiconductor transistor layers share common source and drain electrodes. This consolidation achieves longer effective channel lengths to mitigate short-channel effects while reducing the number of separate electrode structures, thereby managing device complexity.
Solution Approach 2:
The vertically stacked oxide semiconductor transistor layers share common source and drain electrodes, making these electrodes multi-functional. This universality reduces the total number of electrodes needed compared to separate planar transistors, offsetting the increased vertical structural complexity and simplifying the overall device design.
Data Source
AI summary
An embodiment inverter circuit includes a first-conductivity-type semiconductor layer disposed over an interlayer dielectric layer, a gate electrode disposed over the first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer disposed over the gate electrode, a first gate dielectric layer disposed between the first-conductivity-type semiconductor layer and the gate electrode, a second gate dielectric layer disposed between the gate electrode and the second-conductivity-type semiconductor layer, a first source electrode that is in contact with the first-conductivity-type semiconductor layer, a second source electrode that is in contact with the second-conductivity-type semiconductor layer, and a shared drain electrode that is in contact with the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer. At least one of the first-conductivity-type layer and the second-conductivity-type layer includes a metal-oxide semiconductor and/or a multi-layer structure formed in a BEOL process that may be incorporated with other BEOL circuit components such as capacitors, inductors, resistors, and integrated passive devices.