Back-End-of-Line E-Fuse Sub-Lithographic Via Design

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Solution Overview

Problem

Conventional back-end of the line (BEOL) e-fuses face challenges in programming reliability and current leakage due to high programming current requirements and susceptibility to void formation in tight pitch interconnect layers, where lithography limitations prevent the formation of smaller cross-section vias, leading to increased manufacturing complexity and cost.

Innovation Solution

A BEOL e-fuse structure with a sub-lithographic via is formed between conductive features, using a line-first dual damascene scheme and offset patterning to create a sub-lithographic via dimension, allowing for reliable programming by electromigration and reducing current leakage, with the via's cross section tuned to match the target programming current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional BEOL e-fuse structure with standard lithographic via is used, then manufacturing process is simpler, but programming current requirement increases and reliability decreases

Engineering Contradiction:
Improveprogramming reliabilityVSAvoidprogramming current
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies local quality by creating a via with non-uniform cross-section along its length. The via has a first cross-sectional area at the via/line interface and a second cross-sectional area at the via/via interface, with the ratio between them optimized to concentrate current density locally at the via/line interface. This local concentration of current density enables reliable fuse programming with reduced overall programming current requirements.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the geometric parameters of the via structure by forming it with different cross-sectional areas at different heights. The via cross-sectional area is tuned as a critical parameter to achieve the desired current density distribution. By optimizing the via cross-sectional area ratio, the patent achieves effective fuse programming at lower current levels while improving reliability.

Inventive Principle:
Principle #35Parameter changes

2Use of energy by moving object

If via cross section is reduced to concentrate current density, then programming current requirement decreases, but lithography capability is exceeded at tightest pitch levels

Engineering Contradiction:
Improveprogramming currentVSAvoidvia dimension control
Core Design Contradiction:
Use of energy by moving objectVSManufacturing precision

Solution Approach 1:

The patent resolves the lithography limitation by transitioning from a two-dimensional via cross-section problem to a three-dimensional solution. Instead of reducing the via cross-sectional area in the planar dimension (which is constrained by lithography pitch), the patent varies the via cross-sectional area in the vertical dimension. The via has different cross-sectional areas at different heights, allowing current density concentration without requiring sub-lithographic planar dimensions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent applies preliminary action by forming the via structure with controlled non-uniform cross-section during the via formation process itself, before the fuse programming step. The via is engineered with the optimal cross-sectional area profile in advance, using deposition and etch processes that create the desired geometry. This preliminary structuring ensures that when programming current is applied, the current density is already concentrated at the correct location, enabling reliable programming with reduced current.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If via is misaligned to reduce contact area, then current density concentrates, but structure becomes susceptible to current leakage and manufacturing complexity increases

Engineering Contradiction:
Improvecurrent density concentrationVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies asymmetry by creating a via with an asymmetric cross-sectional profile. The via cross-sectional area varies along its length, being smaller at the via/line interface and larger at the via/via interface. This asymmetric geometry naturally concentrates current density at the via/line interface without requiring lateral misalignment. The symmetric lateral alignment is maintained, simplifying the manufacturing process while achieving the desired current density concentration through the asymmetric vertical profile.

Inventive Principle:
Principle #4Asymmetry

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables reliable and efficient programming of BEOL e-fuses in tightest pitch layers with reduced current requirements and improved yield by forming a sub-lithographic via, minimizing void formation in the via and preventing current leakage to adjacent features, thus enhancing manufacturing reliability and cost-effectiveness.

Implementation Method 1

use the phenomenon of electromigration (EM) to program the fuses

Methodology Applied
Scientific EffectElectromigration:

Data Source

PatentUS9893011B2Back-end electrically programmable fuse
Publication Date: 2018.02.13 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US9893011B2 patent drawing
  • US9893011B2 patent drawing
  • US9893011B2 patent drawing

AI summary

A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.