BEOL Feedback Gain Cell Layout for Data Retention and Fast Access
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Solution Overview
Problem
Gain cell embedded memory technologies face challenges in data retention, threshold voltage variability, memory access time, and device footprint reduction, limiting their performance and scalability.
Innovation Solution
Implementing a 5-transistor gain cell circuit with at least one feedback transistor formed in the back-end-of-line (BEOL) to enhance storage node charge retention, reduce device footprint, and improve memory access time, using BEOL-compatible materials such as amorphous oxides and carbon nanotubes for the BEOL transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional SRAM cells are used, then faster access speeds and robust static data retention are achieved, but higher power consumption and larger device footprint occur
Solution Approach 1:
The patent merges the feedback transistor with the existing gain cell structure by integrating it into the BEOL layer, creating a hybrid 5T gain cell that combines the retention capability of SRAM with the low power characteristics of gain cell architecture
Solution Approach 2:
The feedback transistor is placed in the BEOL (back-end-of-line) layer above the FEOL transistors, utilizing the vertical dimension to add retention functionality without increasing the planar footprint, thereby maintaining compact device size while improving data retention
2Area of stationary object
If gain cell embedded memory is used, then smaller device footprint and lower power consumption are achieved, but data retention and threshold voltage variability improve insufficiently
Solution Approach 1:
The feedback transistor creates a feedback path from the storage node back to itself through the BEOL layer, forming a regenerative feedback loop that actively maintains the stored charge state and improves data retention by compensating for leakage currents
Solution Approach 2:
By placing the feedback transistor in the BEOL layer above the FEOL transistors, the patent utilizes the vertical dimension to add retention functionality without increasing the planar footprint, thereby maintaining compact device size while improving data retention
3Use of energy by moving object
If gain cell embedded memory is used, then lower power consumption is achieved, but memory access time and device footprint reduction are insufficient
Solution Approach 1:
The patent segments the transistor functions by placing read and write transistors in FEOL (front-end-of-line) for fast operation, while separating the feedback transistor in BEOL (back-end-of-line) for retention, allowing each component to be optimized for its specific function without compromising overall performance
Data Source
AI summary
One aspect of the present disclosure pertains to a device. The device includes a first transistor and a second transistor coupled in series; a third transistor and a fourth transistor coupled in series; and a fifth transistor, a first terminal of the fifth transistor being coupled to each of a first terminal of the first transistor and a first terminal of the second transistor, and a control terminal of the fifth transistor being coupled to a second terminal of the second transistor at a storage node. A control terminal of the fourth transistor is coupled to the storage node, and at least one of the first to fifth transistors is located in a layer above another one of the first to fifth transistors.