BEOL Interconnects via Selective Barrier Etching

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current back end of line (BEOL) integration for interconnects faces challenges such as starting with higher trench heights due to barrier planarization, resulting in smaller grains, metallization voids, and poor conformality, which can lead to feature loss.

Innovation Solution

The method involves forming trenches with a target post-planarization height, replacing barrier planarization with selective cap layer deposition and wet etch removal to minimize feature loss, and using a diffusion barrier layer with cap layers to enhance conformality and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Shape

If barrier planarization is used to form diffusion barrier layers, then planarity is improved, but trench height increases resulting in smaller grains, metallization voids, and poor conformality

Engineering Contradiction:
ImproveplanarityVSAvoidconformality
Core Design Contradiction:
ShapeVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming the diffusion barrier layer to the desired final thickness before trench formation. This allows the barrier layer to be deposited with optimal conformality and grain structure, eliminating the need for subsequent planarization that would compromise these properties. The barrier layer is formed in advance with precise thickness control, ensuring both good conformality and avoiding metallization voids.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent inverts the conventional sequence by forming the diffusion barrier layer before the trenches rather than after. This reversal allows the barrier layer to be deposited conformally on the trench walls and floor simultaneously, ensuring uniform thickness and avoiding the planarity issues that arise when planarization is applied after trench formation. The inversion of the process sequence resolves the contradiction between planarity and conformality.

Inventive Principle:
Principle #13The other way round (Inversion)

2Shape

If higher trench heights are used to accommodate barrier planarization, then planarity is improved, but grain size decreases and metallization voids form

Engineering Contradiction:
ImproveplanarityVSAvoidinterconnect reliability
Core Design Contradiction:
ShapeVSReliability

Solution Approach 1:

The diffusion barrier layer is formed to the final desired thickness before trench formation, ensuring optimal grain structure and eliminating the need for excessive trench height. This preliminary formation allows the barrier layer to achieve its target thickness with proper conformality, avoiding metallization voids and maintaining interconnect reliability without requiring higher trenches for subsequent planarization.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the process parameter sequence by depositing the barrier layer to its final thickness parameter before trench formation, rather than depositing a thicker layer and subsequently removing material through planarization. This parameter change ensures optimal grain size and eliminates metallization voids while maintaining the required planarity, thereby improving interconnect reliability.

Inventive Principle:
Principle #35Parameter changes

3Shape

If barrier planarization is performed, then surface flatness is improved, but feature loss occurs

Engineering Contradiction:
Improvesurface flatnessVSAvoidfeature integrity
Core Design Contradiction:
ShapeVSManufacturing precision

Solution Approach 1:

The diffusion barrier layer is formed to the exact final desired thickness before trench formation, eliminating the need for subsequent planarization processes. This preliminary action ensures that the barrier layer achieves optimal surface flatness and conformality simultaneously, without causing feature loss that would occur if material were removed in a later planarization step.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts the planarization step from the process sequence by forming the barrier layer to its final thickness in advance. This removal of the planarization operation eliminates the harmful effect of feature loss while maintaining the necessary surface flatness, as the barrier layer is deposited conformally with the correct thickness from the beginning.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for larger grains and improved barrier/liner/seed conformality, reducing feature loss and enhancing the reliability of interconnects during BEOL integration.

Implementation Method 1

forming one or more interconnects by depositing conductive material on a diffusion barrier layer in respective ones of one or more trenches formed within an interlevel dielectric

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Implementation Method 2

forming one or more cap layers on respective ones of the one or more interconnects, and selectively etching the diffusion barrier relative to the one or more cap layers

Methodology Applied
Scientific EffectSelective deposition: Deposition (physical)

Data Source

PatentUS10699945B2Back end of line integration for interconnects
Publication Date: 2020.06.30 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10699945B2 patent drawing
  • US10699945B2 patent drawing
  • US10699945B2 patent drawing

AI summary

A method for back end of line (BEOL) integration for one or more interconnects includes forming one or more interconnects by depositing conductive material on a diffusion barrier layer in respective ones of one or more trenches formed within an interlevel dielectric, forming one or more cap layers on respective ones of the one or more interconnects, and selectively etching the diffusion barrier relative to the one or more cap layers to remove portions of the diffusion barrier layer along the interlevel dielectric.