BEOL Embedded Multi-Memory Interconnect for Smaller ICs
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Solution Overview
Problem
The challenge in semiconductor integrated circuit (IC) manufacturing is to reduce chip size and manufacturing costs while maintaining high performance by integrating memory devices into the back-end-of-line (BEOL) process, thereby releasing the front-end-of-line (FEOL) area for advanced node adoption and shortening data/signal transmission distances.
Innovation Solution
The integration of multiple memory devices, including Non-Volatile Memory (NVM), high density cache, and One-time Programmable (OTP) devices, is achieved through a BEOL process, where these devices are embedded in dielectric layers of the interconnect structure, allowing for reduced chip size and cost-effective manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If memory devices are integrated into the BEOL process, then chip size is reduced and FEOL area is released for advanced nodes, but manufacturing process complexity increases
Solution Approach 1:
The patent merges multiple memory device types (NVM, cache, OTP) into a single integrated memory module that is embedded within the BEOL interconnect structure. This consolidation reduces the overall chip area by eliminating separate fabrication processes and integrating diverse memory functions into one unified structure during the back-end manufacturing stage.
Solution Approach 2:
The patent transitions from planar memory device integration to three-dimensional embedding within dielectric layers. Memory devices are positioned at different vertical levels and embedded within multiple dielectric layers of the interconnect structure, utilizing the third dimension (vertical stacking) to reduce footprint while maintaining manufacturing feasibility through standardized BEOL processes.
2Ease of manufacture
If multiple memory devices are integrated into the BEOL process, then manufacturing costs are reduced, but device integration complexity increases
Solution Approach 1:
The patent creates a universal memory module platform that can accommodate multiple types of memory devices (NVM, cache, OTP) using the same BEOL integration process. This multi-functional design allows manufacturers to produce different memory configurations through a single standardized process flow, reducing tooling costs and simplifying manufacturing while handling diverse memory device requirements.
Solution Approach 2:
The patent performs preliminary preparation of memory devices and interconnect structures before final integration. Dielectric layers are pre-formed with embedded memory devices, and interconnect patterns are pre-configured to accommodate multiple memory types. This preliminary structuring simplifies the final assembly process and reduces integration complexity by establishing a ready-made framework for memory module incorporation.
3Reliability
If memory devices are embedded in dielectric layers, then data transmission distance is shortened and performance is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces dielectric layers as intermediary structures that facilitate precise positioning of memory devices within the interconnect architecture. These dielectric layers serve as standardized embedding matrices with pre-defined vias and contact structures, acting as mediators between memory devices and interconnect lines. This intermediary approach standardizes the embedding process and reduces precision requirements by providing a controlled, repeatable fabrication environment.
Solution Approach 2:
The patent employs repeated, identical dielectric layer structures and embedding patterns across the chip. Each memory device is embedded using the same standardized process sequence and structural template, creating copies of proven, well-characterized interfaces. This copying approach ensures consistent transmission characteristics and reduces manufacturing precision challenges by eliminating the need to optimize each embedding instance uniquely.
Data Source
AI summary
An integrated circuit includes a substrate, a first transistor, and an interconnect structure. The first transistor is over the substrate. The interconnect structure is disposed on the substrate and includes a first dielectric layer and a memory module. The memory module includes a first memory device, a second memory device, and a third memory device. The first memory device is embedded in the first dielectric layer. The second memory device is disposed aside the first memory device and is embedded in the first dielectric layer. The first memory device, the second memory device, and the third memory device are different types of memory devices.