Raised Source/Drain Oxide TFT Layout for BEOL Contact Resistance
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturizing transistors further due to high contact resistance between metal and thin film oxide semiconductors, which hampers the integration of thin film transistors (TFTs) in the back-end-of-line (BEOL) for increased areal density and functionality, as current TFTs have insufficient switching speed for core logic tasks.
Innovation Solution
The integration of raised source/drain oxide semiconducting thin film transistors in the BEOL, utilizing a combination of thick Indium-Tin-Oxide (ITO) layers for metallic properties and thin ITO layers for semiconducting properties, along with other oxides like Indium-Gallium-Zinc-Oxide (IGZO), to reduce parasitic resistance and optimize channel performance independently of source/drain design, without the need for doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If thin film oxide semiconductors are used in TFTs for BEOL integration, then low processing temperature is achieved, but high contact resistance occurs between metal and thin film oxide semiconductors
Solution Approach 1:
The patent applies local quality by using different thicknesses of oxide semiconductor layers in different regions: a first thickness in the channel region and a second thickness (greater than the first) in the source/drain regions. This local variation optimizes both low-temperature processing compatibility and electrical contact performance in respective regions.
Solution Approach 2:
The patent employs composite materials by combining multiple oxide semiconductor layers with different compositions and thicknesses. The structure includes a first oxide semiconductor layer and a second oxide semiconductor layer with different thicknesses, creating a composite structure that simultaneously achieves low processing temperature and reduced contact resistance.
2Area of stationary object
If transistor size is reduced to increase areal density, then chip area is optimized, but switching speed becomes insufficient for core logic tasks
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional raised source/drain structures. By raising the source/drain regions above the substrate plane, the invention increases functional volume without proportionally increasing footprint area, thereby maintaining switching performance while improving areal density.
Solution Approach 2:
The patent changes physical parameters by varying the thickness of oxide semiconductor layers in different regions. The channel region has a first thickness optimized for switching speed, while source/drain regions have a greater second thickness optimized for contact properties, allowing simultaneous optimization of both speed and density.
3Area of stationary object
If peripheral transistors are moved from FEOL to BEOL, then valuable chip area is freed in FEOL, but functionality addition at BEOL is limited
Solution Approach 1:
The patent makes BEOL structures multi-functional by designing raised source/drain TFTs that can simultaneously serve as peripheral devices and core logic elements. The enhanced three-dimensional structure provides sufficient switching performance for core logic tasks, allowing BEOL to perform multiple functions previously restricted to FEOL.
Solution Approach 2:
By moving from planar to raised three-dimensional structures in BEOL, the patent enables peripheral transistors to achieve core logic-level performance. The vertical dimension provides additional functional capability, allowing BEOL devices to handle both peripheral control and core processing tasks.
Data Source
AI summary
A transistor, integrated semiconductor device and methods of making are disclosed. The transistor includes a patterned gate electrode, a dielectric layer located over the patterned gate electrode and a patterned first oxide semiconductor layer comprising a channel region and source/drain regions located on sides of the channel region. The thickness of the source/drain regions is greater than a thickness of the channel region. The transistor also includes contacts located on the patterned first oxide semiconductor layer and connected to the source/drain regions of the patterned first oxide semiconductor layer.