Semiconductor BEOL Trench Width Ratio Optimization
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Solution Overview
Problem
The yield rate of semiconductor devices is significantly lowered due to suboptimal process conditions in the BEOL process, particularly caused by slot dependency, bridge type defects, and uneven failure rates across the wafer, leading to inconsistencies in the SRAM yield rate.
Innovation Solution
Optimizing the BEOL process by adjusting the width ratio of trenches to insulating layers between 0.45 to 0.55, increasing the cell space CD by approximately 10 nm, and refining the RIE process conditions, such as adjusting CHF3 amounts and fence removal times, to reduce serration phenomena and bridge defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the BEOL process conditions are not optimized, then the manufacturing process can be completed, but the yield rate is significantly lowered
Solution Approach 1:
The patent optimizes the width ratio of insulating layers between adjacent trenches to a specific range (0.185 μm to 0.225 μm, or 0.45 to 0.55 ratio) to improve yield rate. This parameter optimization addresses the inconsistency in process conditions across different wafer slots, thereby resolving the contradiction between completing the manufacturing process and achieving high yield rate.
2Reliability
If the insulating layer width between trenches is not controlled within the optimal range, then the BEOL process can proceed, but bridge defects and serration phenomena occur
Solution Approach 1:
The patent specifies precise parameter ranges for insulating layer width (0.185 μm to 0.225 μm) and width ratio (0.45 to 0.55) to prevent bridge defects and serration phenomena during the BEOL process. By controlling these geometric parameters, the patent eliminates defects while maintaining manufacturability.
3Reliability
If slot dependency is present in the BEOL process, then wafer processing can be completed, but uneven failure rates across the wafer occur
Solution Approach 1:
The patent addresses slot dependency by optimizing local geometric parameters (insulating layer width and ratio) specifically in critical areas between trenches. This local optimization ensures uniform process conditions across different wafer slots, eliminating the uneven failure rates caused by slot dependency while maintaining overall process completeness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the SRAM yield rate by 26%, achieving consistent yield rates across the wafer with minimal differences between the center and peripheral areas, thereby improving overall semiconductor device yield.
Implementation Method 1
forming a plurality of trenches by selectively etching the insulating layer
Implementation Method 2
refining the RIE process conditions, such as adjusting CHF3 amounts and fence removal times, to reduce serration phenomena
Data Source
AI summary
Disclosed are embodiments relating to a method of manufacturing a semiconductor device that may improve the yield rate of the semiconductor device. In embodiments, the method may include preparing a substrate including a plurality of conductive patterns, forming first and second insulating layers on the substrate, forming a plurality of via holes by selectively etching the first and second insulating layers, forming a plurality of trenches by selectively etching the second insulating layer in such a manner that the trenches are communicated with the trenches, and forming metal interconnections in the via holes and the trenches. The width ratio of the trench to the insulating layer positioned between adjacent trenches may be in a range of 0.45 to 0.55.