BEOL Wire-Level Layout for Regional Resistance-Capacitance Tuning
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Solution Overview
Problem
Existing semiconductor IC device fabrication technologies face challenges in effectively tuning resistance and capacitance within the BEOL section, leading to suboptimal performance due to uniform wiring dimensions across different regions.
Innovation Solution
The method involves creating distinct vertical dimensions between wiring levels in different regions of the BEOL section, with one region having a greater vertical dimension than the other, allowing for tailored resistance and capacitance by recessing the interlayer dielectric around specific vias and forming top wires to wrap around these vias, thereby inset within the top wire.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform wiring dimensions are used across all BEOL regions, then manufacturing simplicity is maintained, but resistance and capacitance performance is suboptimal
Solution Approach 1:
The patent applies local quality by creating different vertical dimensions between wiring levels in different BEOL regions. Specifically, a first region has a first vertical dimension between bottom and top wire levels, while a second region has a second vertical dimension that is less than the first. This allows each region to be optimized for its specific electrical performance requirements, with the first region providing greater capacitance and the second region providing lower capacitance and resistance.
2Reliability
If vertical dimension between wiring levels is increased in one region, then capacitance is optimized in that region, but manufacturing complexity increases
Solution Approach 1:
The patent segments the BEOL section into multiple regions with different vertical dimensions between wiring levels. The first region maintains a greater vertical dimension for optimized capacitance, while the second region has a reduced vertical dimension. This segmentation is achieved through selective recessing of the interlayer dielectric in specific regions, allowing capacitance optimization without requiring complete redesign of the entire manufacturing process.
3Reliability
If interlayer dielectric is recessed around specific vias, then capacitance is reduced in that region, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by forming the interlayer dielectric to different heights in different regions before completing the wiring structure. The interlayer dielectric is recessed in the second region prior to forming the top wire, creating a stepped structure that pre-determines the final vertical dimension. This preliminary differentiation allows for controlled capacitance values without requiring ultra-precise recessing operations during later manufacturing stages.
Data Source
AI summary
A semiconductor integrated circuit (IC) device includes a bottom wire level, a top wire level, a first region with a first vertical dimension between the bottom wire level and the top wire level, and a second region with a second vertical dimension between the bottom wire level and the top wire level that is less than the first vertical dimension. The discrepancy in the vertical dimensions between wiring levels in different regions of the semiconductor IC device may provide desired or optimized capacitance and/or resistance metrics therein and may increase overall semiconductor integrated circuit (IC) device performance.