BGA Package Isolation Region for Molding Delamination
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Solution Overview
Problem
Conventional ball grid array (BGA) semiconductor packages face issues with delamination between the semiconductor chip and the lower molding layer, leading to defects and reliability concerns due to the small contact area and pressure exerted by the epoxy molding compound.
Innovation Solution
The introduction of an isolation region on the printed circuit board (PCB) with wider outer isolation regions, which facilitates a larger contact area between the upper and lower molding layers, reducing pressure and preventing delamination, and includes a method of forming the semiconductor package by preparing the PCB, forming isolation regions, mounting the semiconductor chip, and molding the epoxy molding compound.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional BGA package structure is used with a molding layer covering the semiconductor chip and wires, then the package achieves high mounting density and minimized electrical signal transmission path, but delamination occurs between the upper molding layer and lower molding layer due to small contact area
Solution Approach 1:
The patent introduces an isolation region that divides the PCB into at least two parts, creating distinct zones for different functional elements. This segmentation allows the molding layer to be positioned in the isolation region, thereby increasing the contact area between the upper and lower molding layers without expanding the overall package footprint, directly addressing the delamination issue caused by insufficient contact area.
Solution Approach 2:
The patent utilizes the isolation region on the PCB surface as an additional spatial dimension to accommodate the molding layer. By positioning the molding layer in the isolation region rather than directly over the chip or wires, the design increases the contact area between molding layers in the planar dimension, preventing delamination while maintaining the compact BGA structure.
2Reliability
If the molding layer is formed to cover the semiconductor chip and wires, then electrical connectivity is achieved, but wire sweeping and shorts occur due to pressure from the epoxy molding compound
Solution Approach 1:
The isolation region segments the PCB structure, creating a dedicated space for the molding layer that is separated from the chip and wire areas. This segmentation reduces the pressure exerted by the molding compound on the wires, preventing wire sweeping and shorts while still achieving the necessary electrical connectivity through the solder balls on the PCB.
Solution Approach 2:
The isolation region acts as an intermediary structure between the chip/wire area and the molding layer. By positioning the molding layer in the isolation region, the design mediates the pressure interaction, allowing the molding compound to set without directly pressing on the wires, thereby preventing wire damage while maintaining package integrity.
3Area of stationary object
If the contact area between upper and lower molding layers is reduced, then the package size can be minimized, but delamination becomes more likely
Solution Approach 1:
The patent exploits the isolation region on the PCB surface as an additional spatial dimension to maximize the contact area between molding layers within the available planar space. By utilizing this dimension effectively, the design achieves optimal molding layer adhesion without increasing the overall package footprint, preventing delamination while maintaining compact dimensions.
Data Source
AI summary
Provided are a semiconductor package, a method of forming the semiconductor package, and a printed circuit board (PCB). The semiconductor package includes: a PCB including at least two parts divided by an isolation region; a semiconductor chip mounted on the PCB; and a molding layer disposed in the isolation region. The method includes: preparing a PCB, the PCB including a plurality of chip regions and a scribe region; forming isolation regions dividing each of the chip regions into two parts, the isolation regions including inner isolation regions and outer isolation regions, the inner isolation regions being provided in the chip regions, the outer isolation regions being provided at both ends of the inner isolation regions so as to extend toward the scribe region; mounting semiconductor chips on the chip regions; and cutting the PCB along the scribe region to divide the chip regions into at least two parts.