Band Gap Reference Startup Control for Stable MEMS Sensor Output
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Solution Overview
Problem
Bipolar junction transistors (BJTs) in band gap reference (BGR) circuits can have parasitic transistors that turn ON during startup due to residual charges, impairing the ability to generate a stable voltage reference, affecting the functionality of MEMS sensors.
Innovation Solution
A sensor assembly with a band gap reference circuit that includes parallel transistors with associated parasitic transistors, using start-up switches to maintain them in an OFF state during initialization, ensuring proper BGR operation by preventing parasitic transistor activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If BJTs are used in BGR circuits to generate stable voltage reference, then voltage reference stability is improved, but parasitic transistors may turn ON during startup and impair circuit functionality
Solution Approach 1:
The startup circuit activates before the main BGR circuit to preemptively disable parasitic transistors. By generating a startup signal that closes switches connected to parasitic transistor bases, the circuit prevents harmful current paths from forming during initialization, ensuring clean startup conditions for the voltage reference generation
Solution Approach 2:
Startup switches act as intermediary elements between the startup circuit and parasitic transistors. These switches are strategically placed to control the base terminals of parasitic transistors, serving as mediators that block harmful current flow without affecting the operation of main signal transistors in the BGR circuit
Data Source
AI summary
A sensor assembly, sensor assembly interface circuit, and a band gap reference circuit are provided. The sensor assembly includes a transducer element disposed in a housing, and an interface circuit disposed in the housing and having an input pad coupled to the transducer element, and an output pad coupled to a host-interface of the housing. The interface circuit further has an analog frontend (AFE) amplifier or buffer located between and coupled to the input pad and output pad. The interface circuit still further has a band gap reference (BGR) circuit, which includes first and second transistors arranged in parallel between a shared voltage source and a substrate of the integrated circuit, and has a common control terminal coupled to the first and second transistors. The BGR circuit further includes first and second parasitic transistors at the substrate, the first parasitic transistor being complementary to and associated with the first transistor, and the second parasitic transistor being complementary to and associated with the second transistor. The interface circuit still further has a start-up circuit configured to turn OFF at least one of the first and second parasitic transistors during startup. An output of the BGR circuit is coupled to the AFE amplifier or buffer.