Bi-directional Weight Cell for Neuromorphic Computing
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Solution Overview
Problem
Performing multiply and accumulate (MAC) operations digitally is expensive, especially for vector-matrix multiplications in neural networks, and there are latency and power penalties due to memory bottlenecks when transferring weights in large neural networks.
Innovation Solution
A weight cell using bi-directional magnetic tunnel junction (MTJ) memory elements with perpendicular magneto anisotropy and diodes in a crossbar array architecture, allowing for analog multiplication and accumulation operations, reducing the need for digital precision and minimizing memory transfer latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital MAC operations are performed, then computational precision is improved, but power consumption and cost increase
Solution Approach 1:
The patent replaces digital computational systems with an analog physical system using Ohm's law and Kirchhoff's current law. The crossbar array uses resistive memory elements where current flow naturally performs multiplication (I=V/R) and accumulation (current summation at output nodes) operations, eliminating the need for digital processing circuits and significantly reducing power consumption.
Solution Approach 2:
The patent changes the operational parameter from digital voltage levels representing binary values to analog resistance values that directly encode weight parameters. This allows the system to perform MAC operations in the analog domain where resistance values continuously represent weight magnitudes, enabling efficient parallel computation without digital conversion overhead.
2Loss of time
If cache/memory is increased to reduce memory bottlenecks, then transfer latency is reduced, but device complexity and area increase
Solution Approach 1:
The patent merges the weight storage function with the computation function by integrating resistive memory elements directly into the crossbar array computing nodes. This unified architecture eliminates separate cache/memory structures, as weights are stored locally at the computation sites and accessed in-place during MAC operations, reducing both latency and architectural complexity.
Solution Approach 2:
The crossbar array architecture enables self-service computation where the weight values stored in resistive memory elements automatically participate in MAC operations without requiring external memory access. The physical properties of the resistive elements (their resistance values) directly enable the computation, eliminating the need for separate memory management infrastructure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient MAC operations with reduced power consumption and latency by encoding matrix values in resistance states of bi-directional memory elements, facilitating faster and more energy-efficient neuromorphic computing and machine learning applications.
Implementation Method 1
first and second bi-directional memory elements each configured to switch between a first resistance state and a second resistance state different than the first resistance state
Implementation Method 2
Each of the first and second bi-directional memory elements may be a magnetic tunnel junction (MTJ) including a pinned layer and a free layer
Implementation Method 3
a first diode in forward bias connecting the second terminal of the first bi-directional memory element to a first output line, a second diode in reverse bias connecting the second terminal of the second bi-directional memory element to a second output line
Implementation Method 4
analog multiplication and accumulation operations
Implementation Method 5
analog multiplication and accumulation operations
Data Source
AI summary
A weight cell including first and second bi-directional memory elements each configured to switch between a first resistance state and a second resistance state different than the first resistance state. A first input line is connected to a first terminal of the first bi-directional memory element, and a second input line is connected to the first terminal of the second bi-directional memory element. A first diode in forward bias connects the second terminal of the first bi-directional memory element to a first output line, a second diode in reverse bias connects the second terminal of the second bi-directional memory element to a second output line, a third diode in reverse bias connects the second terminal of the first bi-directional memory element to the second output line, and a fourth diode in forward bias connects the second terminal of the second bi-directional memory element to the first output line.