Bi-processor architecture for secure smart card systems

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Smart cards are vulnerable to hacker attacks that exploit encryption algorithms and reverse engineering, allowing unauthorized access to sensitive information due to the central processing unit's unencrypted access to program memory and potential manipulation.

Innovation Solution

A bi-processor system is implemented, where a first CPU handles non-sensitive tasks and a second CPU, with a separate power source, memory, and hardware shield, handles sensitive information, communicating through a secure interface that prevents direct access or control by the first CPU.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single CPU is used to handle all tasks including sensitive information processing, then device complexity is reduced, but security is compromised due to unencrypted access to program memory

Engineering Contradiction:

ImprovesecurityVSAvoiddevice complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The system is divided into two separate CPUs: a first CPU for non-sensitive tasks and a second CPU for sensitive information processing. This segmentation isolates sensitive operations from potential attacks on the main processor, resolving the contradiction by prioritizing security while accepting increased device complexity as a necessary trade-off.

Inventive Principle:

Principle #1Segmentation

2Reliability

If encryption is applied to program memory to protect sensitive information, then security is improved, but access speed and processing efficiency deteriorate

Engineering Contradiction:

ImprovesecurityVSAvoidaccess speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The sensitive information processing functions are extracted from the main CPU and placed in a separate second CPU. This allows the main system to maintain unencrypted fast access for non-sensitive operations, while the dedicated secure processor handles encryption/decryption operations, thus improving security without significantly impacting overall system speed.

Inventive Principle:

Principle #2Taking out (Extraction)

3Reliability

If hardware countermeasures such as memory encryption are implemented, then protection against reverse engineering is improved, but the CPU's ability to access and manipulate memory contents for legitimate functions deteriorates

Engineering Contradiction:

Improveprotection against reverse engineeringVSAvoidmemory access capability

Core Design Contradiction:

ReliabilityVSEase of operation

Solution Approach 1:

A secure interface acts as an intermediary between the first CPU and the second CPU's memory space. This mediator enables controlled access where the first CPU can request data processing services without gaining direct access to the encrypted memory contents, thus providing both protection against reverse engineering and maintained operational capability through the mediation layer.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentEP2052344B1Bi-processor architecture for secure systems

Publication Date: 2017.09.27 INSIDE SECURE

Figure 1
Figure 2
Figure 3A~3B

AI summary

Systems, methods and program products for a first central processing unit (CPU) configured to perform tasks that do not require manipulation of sensitive information and a second CPU that is configured to perform tasks that manipulate the sensitive information on behalf of the first CPU. The first CPU and the second CPU can communicate through a secure interface. The first CPU cannot access the sensitive information within the second CPU.