Bias Current Circuit Voltage Adaptation for Low-Voltage Operation
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Solution Overview
Problem
Conventional bias current circuits face performance impairment at low supply voltages due to voltage drops below transistor threshold voltages, making them unsuitable for low-voltage and low-power applications.
Innovation Solution
A bias current circuit design incorporating a supply voltage adapting unit with a third MOS transistor, pull-up, and pull-down current sources, which maintains a voltage difference between nodes to ensure the circuit operates effectively across a wide voltage range by adjusting the source-drain voltage of the third MOS transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the supply voltage VCC is decreased to reduce power consumption, then low-power operation is achieved, but the voltage drop from VCC to node NET2 and the voltage at node NET1 approach or drop below the threshold voltages of the transistors, causing circuit performance impairment
Solution Approach 1:
The patent introduces a third MOS transistor connected between node NET1 and node NET2 as an intermediary element. This transistor acts as a mediator to adjust the voltage distribution between the two nodes, ensuring that both nodes maintain sufficient voltage levels above their respective transistor threshold voltages even when the supply voltage is reduced for low-power operation.
Solution Approach 2:
The patent dynamically adjusts the source-drain voltage of the third MOS transistor based on the supply voltage level. By changing the voltage parameters at nodes NET1 and NET2 through controlled adjustment of the third transistor's operating state, the circuit maintains reliable operation across a wide voltage range while enabling low-power mode when appropriate.
2Temperature
If the supply voltage VCC is decreased for low-voltage operation, then voltage reduction is achieved, but the voltages at nodes NET1 and NET2 become insufficient to maintain proper transistor operation
Solution Approach 1:
The third MOS transistor serves as a voltage mediation device between nodes NET1 and NET2. It actively manages the voltage distribution to ensure that even when the supply voltage is reduced, both nodes maintain adequate voltage levels for proper transistor operation, thus preserving circuit operability under low-voltage conditions.
Solution Approach 2:
The circuit employs dynamic voltage adjustment through the third MOS transistor whose source-drain voltage is adaptively controlled. This dynamic response allows the circuit to automatically adapt to varying supply voltage levels, maintaining proper operation across both high and low voltage conditions without requiring manual intervention or circuit redesign.
3Device complexity
If a conventional bias current circuit design is used, then the circuit structure is simple, but the operating voltage range is limited to high voltages only
Solution Approach 1:
The third MOS transistor is integrated into the existing bias current circuit structure to provide multi-functional capability. It enables the circuit to operate reliably across both high-voltage and low-voltage conditions, transforming a high-voltage-specific circuit into a universal bias current circuit that adapts to various supply voltage levels without requiring completely different circuit architectures.
Solution Approach 2:
The patent segments the voltage management function by introducing a dedicated third MOS transistor that specifically handles voltage adjustment between nodes NET1 and NET2. This segmentation allows the original bias current generation functionality to remain intact while adding independent voltage adaptation capability, thus expanding the operating voltage range with minimal structural modification.
Data Source
AI summary
A bias current circuit which includes: a main unit including first PMOS and NMOS transistors constituting a first current path, and second PMOS and NMOS transistors constituting a second current path together with a first resistor; an output unit; and a supply voltage adapting unit including a third MOS transistor, a pull-up current source and a pull-down current source. The third MOS transistor is connected between a first node to which gates of the first and second PMOS transistors are connected and a second node to which drains of the second NMOS and PMOS transistors are connected. The pull-up current source is mirrored to the first PMOS transistor and configured to provide a current equal to a current provided by the pull-down current source. The bias current circuit has an operating voltage range encompassing low-voltage band such that it is operable at high and low voltages.