Logic Circuits TRIZ Cases

A microbump-linked parallel interface speeds programmable logic configuration by moving data across stacked die with NOC, sector parallelism, and pipelining.

Common DSP functions move into hardened circuits while programmable logic handles custom tasks, reducing power, die pressure, and heat.

Output voltage clamping and current suppression let a logic circuit run without a separate power source circuit, cutting chip area and power use.

Hardwired logic parses network frames and writes only payload data, enabling direct FPGA booting without JTAG delays or auxiliary processors.

Segmented IC routing and pass-gate isolation keep configuration data and clock access available when neighboring regions are powered down.

Hybrid 27×18 and 12×12 multipliers make FPGA DSP blocks more flexible for varied digital computations without losing processing capability.

A wireless communication block delivers FPGA configuration bitstreams remotely, eliminating host cable dependence for reprogramming and debugging.

A checkerboard switch box layout cuts FPGA interconnect area and complexity while preserving routeability and CLB access.

A crossover TFT topology switches between diode-load and zero-VGS modes to cut static power while preserving logic speed.

An FPGA bridge decodes instructions and handles I/O so a swappable ASIC can focus on deterministic execution with lower redesign cost and latency.

Adjacent FPGA logic blocks pass lookup table configurations on a shared clock, enabling rapid reconfiguration without power cycling.

Sequential FPGA tile routing across logic-tile subsets resolves interconnect conflicts and congestion while preserving end-to-end signal paths.

Selective via sites and jumpers let one IC architecture switch between FIFO and deserializer functions while cutting photomask count and silicon area.

Low-precision high-dynamic-range arithmetic raises parallel throughput, then adds limited high-precision computing to improve search quality.

Common DSP functions move into hardened circuits while programmable logic handles custom tasks, cutting resource use, die area, and power.

Low-precision high-dynamic-range arithmetic increases parallel search throughput, while limited high-precision steps improve result quality.

A mesh clock fabric with per-tile clock generation and mux selection aligns FPGA tile clocks despite phase and frequency variation.

Cascade frame incrementers and a row controller speed frame allocation in programmable circuits while removing flag circuitry overhead.

Low-precision high-dynamic-range arithmetic increases operations per transistor by shrinking arithmetic elements for dense parallel computing.

A crossover TFT topology uses zero-VGS load operation to cut unipolar logic power draw while preserving speed and simpler circuit structure.

Common-mode voltage modulation adds bidirectional data over differential video links while limiting interference and reflections.

Reset re-timing across multi-channel TX lanes cuts skew to within one unit interval, easing receiver de-skew at high data rates.

Using dual-rail null convention logic, these gates self-indicate valid data and remove clock distribution to cut power and timing complexity.

Latch-based pipelining lets Clock Guided Logic alternate precharge and evaluation phases to balance stage delays and raise throughput.

Flexible DSP slice routing and selective latching cut latency between PLD rows while supporting cascaded multipliers and ALU operations.

Word-oriented arithmetic blocks improve PLD DSP density and frequency while lowering power, cost, and interconnect complexity.

Integrated pre-adder MACC logic speeds symmetric FIR filter implementation in PLDs while cutting CLB usage and power.

A pulsed-clock domino stage and feedback output path cut data-to-output delay while preserving register stability in noisy, leaky pipelines.

Multi-stage dynamic logic and pulse latching remove keeper delay while preserving noise resistance and leakage robustness in fast CPU gating.

Using only three clocked transistor gates and a low-frequency keeper clock, this flip-flop cuts clock energy while staying robust to process variation.

Split evaluation units and limited voltage swing improve domino logic noise immunity at low supply voltage while reducing power.

A dual-trigger static flip-flop cuts clock-switched capacitance and keeps stable nodes from toggling, improving process-robust data storage.

A self-resetting domino gate removes clock routing by using RTS input behavior to trigger evaluation, latch, and reset locally.

Removes clock routing from domino logic by using return-to-state inputs for self-timed evaluation and automatic reset, improving speed and power use.

A high-Vt PMOS sleep transistor cuts subthreshold and gate oxide leakage in idle domino logic while limiting area and energy overhead.

A ring-oscillator PMV uses programmable memory cell drive current to characterize process variation and available write margin.

Split PMOS feedback and charge-supply paths suppress output glitches while preserving high-speed low-voltage circuit operation.

A bias current circuit uses a supply voltage adapting unit to maintain operation across wide voltage ranges.

Vertical IO columns bypass fabric breaks, boosting density while preserving signal integrity.

Tying PMOS bodies to a bias voltage lower than the supply maintains transistor operation and driving capability when output voltage drops.