Coupled FPGA Lookup Tables for Rapid Reconfiguration
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Solution Overview
Problem
Existing field programmable gate arrays (FPGAs) are limited in their ability to rapidly change lookup table configurations, resulting in slow operation frequency changes, typically occurring only hundreds of times per second, due to the need to cycle power for each configuration modification.
Innovation Solution
Coupling logic blocks in FPGAs allows direct transfer of lookup table configurations between adjacent blocks, utilizing non-volatile CMOS-based memory cells to reduce power consumption and enable faster operation frequency changes, potentially up to millions or billions of times per second, by leveraging a common global clock signal to update configurations without powering down the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If lookup table configurations are loaded by cycling power for each configuration modification, then configuration changes can be made, but the operation frequency changes are slow (hundreds of times per second)
Solution Approach 1:
The patent pre-loads configuration data into on-chip memory blocks before operation. This preliminary action allows the FPGA to switch between configurations rapidly by simply selecting different pre-loaded data blocks, eliminating the need for slow external memory access or power cycling during operation. The configuration data is prepared in advance and stored locally, enabling fast reconfiguration.
Solution Approach 2:
The patent introduces on-chip memory blocks as an intermediary between external configuration sources and the lookup tables. This intermediary component buffers configuration data locally, allowing rapid access and switching without directly accessing external memory or requiring power cycles. The on-chip memory acts as a mediator that decouples the slow external configuration process from the fast internal reconfiguration needs.
2Adaptability or versatility
If configuration data is stored in external memory and loaded each time, then configuration flexibility is maintained, but access time increases and speed decreases
Solution Approach 1:
The patent segments configuration data into multiple blocks, with frequently accessed configurations stored in on-chip memory and less frequently accessed configurations stored in external memory. This segmentation allows the system to maintain configuration flexibility by keeping all configurations available while enabling fast access to commonly used configurations through local storage.
Solution Approach 2:
The patent implements local quality by placing different types of configuration data in different storage locations based on access frequency. Hot configurations are stored locally in on-chip memory for fast access, while cold configurations remain in external memory. This local optimization maintains overall system flexibility while dramatically improving the speed of frequent reconfiguration operations.
Data Source
AI summary
A field programmable gate array (FPGA) includes: a first logic block having a first lookup table; and a second logic block having a second lookup table, wherein the first logic block is coupled to the second logic block, in which the first logic block is configured to pass, upon a clock cycle of the FPGA, data about a lookup table configuration stored in the first lookup table to the second logic block.