Reference Buffer Circuit Body Biasing Low Voltage Driving
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Solution Overview
Problem
Conventional reference buffer circuits face challenges in maintaining driving capability when supply voltage is reduced, leading to the second PMOS transistor being turned off and the driving stage ceasing to function due to low output voltage VoutL being lower than the gate-to-source voltage drop.
Innovation Solution
The solution involves modifying the PMOS transistors by tying their bodies to a bias voltage lower than the supply voltage, and increasing the width of the NMOS and PMOS transistors in the driving stage, along with using cascoded NMOS transistors to enhance power supply rejection ratio and maintaining the PMOS transistors operative, thereby ensuring high driving capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If supply voltage is reduced, then power consumption is decreased, but driving capability deteriorates and the circuit stops functioning
Solution Approach 1:
The patent applies body biasing to the PMOS transistor, changing the electrical parameters of the transistor by applying a negative voltage to its body terminal. This modifies the threshold voltage and maintains the transistor in the active region even when supply voltage is reduced, thereby preserving driving capability while enabling lower power consumption operation
Solution Approach 2:
The patent introduces a dynamic body biasing mechanism where the body voltage of the PMOS transistor is controlled to adapt to different operating conditions. This dynamic adjustment allows the transistor to maintain optimal performance across varying supply voltages, ensuring reliable operation at low voltage while preserving driving capability
2Power
If output voltage VoutL drops to maintain low supply voltage, then power consumption is reduced, but the second PMOS transistor turns off and the driving stage ceases to function
Solution Approach 1:
By applying body biasing to the second PMOS transistor (M4), the patent changes its electrical characteristics to maintain it in the active region. The negative body voltage compensates for the reduced gate-to-source voltage, ensuring the transistor remains conductive even when VoutL drops to maintain low power consumption
Solution Approach 2:
The patent applies preliminary body biasing to prevent the PMOS transistor from turning off. By pre-applying a negative voltage to the body terminal, the circuit proactively counteracts the tendency of the transistor to shut down when output voltage drops, maintaining continuous operation at low power levels
Data Source
AI summary
A reference buffer circuit with high driving capability is disclosed. In which, a buffering stage has a first NMOS transistor and a first PMOS transistor to provide high and low tracking voltages respectively based on a high input voltage and a low input voltage. A first driving stage is driven by the high and low tracking voltages to output a first high output voltage and a first low output voltage. A body of the first PMOS transistor is tied to a first bias voltage lower than a supply voltage for the buffering and first driving stages.