Clockless Domino Logic Gate With Self-Reset Return-to-State
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Solution Overview
Problem
Existing logic circuits require a clock signal for operation, which can be impractical in certain integrated circuit applications, especially when logic functions need to be performed at random locations, leading to inefficiencies in power consumption and speed.
Innovation Solution
A clockless return to state domino logic gate is developed, comprising multiple nodes, a domino circuit, an evaluation circuit, an enable circuit, and a reset circuit, allowing nodes to switch between states without a clock signal, enabling self-resetting operations responsive to return to state signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock signal is used to control logic circuits, then the logic operations can be performed with stable timing control, but the power consumption increases and routing complexity increases when logic functions need to be placed at random locations
Solution Approach 1:
The invention extracts and removes the clock signal from the logic circuit operation. The clockless RTS domino logic gate performs logic operations using only RTS signals without requiring a separate clock signal, thereby eliminating the power consumption and routing complexity associated with clock distribution while maintaining reliable operation through the inherent timing characteristics of the RTS signal protocol
Solution Approach 2:
The logic circuit performs self-timing and self-control using the RTS signal transitions. The evaluation circuit automatically detects RTS signal transitions and triggers logic operations without external clock control, and the self-resetting mechanism automatically resets the circuit state after operation, eliminating the need for clock-controlled reset sequences
2Productivity
If logic circuits are placed at random locations on an integrated circuit, then fast logic functions can be performed, but routing a clock signal to these locations becomes difficult and impractical
Solution Approach 1:
The invention removes the clock signal requirement entirely, allowing logic circuits to be placed at any location on the integrated circuit without needing clock signal routing. The clockless RTS domino logic gate uses only RTS signals for operation, eliminating the manufacturing complexity of routing clock signals to random locations while maintaining fast logic function performance
Solution Approach 2:
The RTS signal serves multiple functions simultaneously: it provides input data, timing control, and reset signaling. This multi-functionality eliminates the need for separate clock signal routing, enabling logic circuits to be freely placed at random locations on the integrated circuit without increasing manufacturing complexity
3Use of energy by moving object
If static CMOS gates are used, then power consumption is relatively low, but input capacitance is significant and evaluation contention occurs between complementary P-devices and N-devices making them slow
Solution Approach 1:
The invention uses dynamic domino logic circuits that operate in phases (evaluation phase and reset phase) controlled by RTS signal transitions. The circuit transitions between different operational states dynamically, allowing fast signal propagation during evaluation while consuming low power during reset, achieving both high speed and low power consumption that static CMOS cannot achieve
Solution Approach 2:
The logic circuit operates in periodic cycles triggered by RTS signal transitions, with distinct evaluation and reset phases. This periodic operation allows the circuit to achieve high speed during the evaluation phase when signals propagate quickly, while maintaining low power consumption during the reset phase, resolving the speed-power tradeoff inherent in static CMOS gates
Data Source
AI summary
A clockless return to state domino logic gate is disclosed responsive to multiple return to state input nodes. A domino circuit has a preset state in which it presets a preset node to a second state. The domino circuit switches to a latch state and switches an output node when the preset node is pulled to a first state. The domino circuit resets back to the preset state and switches the output node back to its default state when a reset node is pulled to the second state. An evaluation circuit pulls the preset node to the second state when the input nodes are in an evaluation state. An enable circuit enables a reset condition when the domino circuit is in its latch state. A reset circuit pulls the reset node to the first state after an evaluation event when the input nodes are no longer in the evaluation state.