Dynamic Logic Gate Circuit Without Keeper-Induced Delay
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Solution Overview
Problem
Conventional digital logic circuits using domino gates face challenges in achieving high-speed performance due to limitations in noise resistance, current leakage, and the need for keeper circuits, which can increase gate delay and complicate synthesis and timing analysis.
Innovation Solution
A digital logic circuit design incorporating dynamic logic gates with pre-charge and discharge transistors, pull-down networks, and a pulse signal generating unit that eliminates the need for keeper circuits, allowing for high-speed operation and improved noise resistance by using a pulse latch and delayed clock signals to stabilize the gating output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a domino gate is used to improve operating speed, then the operating speed increases, but the circuit becomes vulnerable to input noise and current leakage
Solution Approach 1:
The logic gate is divided into multiple stages (first dynamic logic gate, second dynamic logic gate) with each stage processing part of the logic function. This segmentation allows better control of signal transitions and reduces vulnerability to noise and leakage in any single stage.
Solution Approach 2:
A pre-charge transistor is used to pre-charge the output node before the actual logic operation. This preliminary action ensures that the output is in a known state and reduces the impact of leakage currents during the evaluation phase, improving noise resistance while maintaining high speed.
2Reliability
If a keeper circuit is added to improve domino gate performance, then noise resistance improves, but gate delay increases largely due to fighting
Solution Approach 1:
The keeper circuit is completely removed from the design. Instead, the patent uses a pulse signal generating unit that provides precise timing control to the second dynamic logic gate, eliminating the need for a keeper circuit and its associated delay and fighting problems.
Solution Approach 2:
The patent uses periodic pulse signals generated by the pulse signal generating unit to control the operation of the second dynamic logic gate. These pulse signals provide precise timing control without requiring a keeper circuit, achieving noise resistance through controlled periodic operation rather than continuous feedback.
3Ease of manufacture
If conventional synthesis manner is used, then static timing analysis is easier, but the number of allowed inputs is limited and operating speed becomes slow
Solution Approach 1:
The patent employs dynamic logic gates instead of static gates, allowing for higher operating speeds. The dynamic nature of the gates enables faster signal transitions and better utilization of the clock signal, achieving high-speed operation while remaining compatible with conventional synthesis and timing analysis methodologies.
4Adaptability or versatility
If more input data are gated in one stage, then logic operation capability improves, but the number of stacks increases and operating speed decreases
Solution Approach 1:
The logic gate is divided into multiple stages (first dynamic logic gate, second dynamic logic gate), with each stage handling a portion of the total input data. This segmentation reduces the number of stacks in any single stage, maintaining fast operation speed while enabling the circuit to process a large number of inputs across the entire logic gate structure.
Data Source
AI summary
A digital logic gate suitable for a high-speed operation of a central processing unit. The digital logic gate comprises the first dynamic logic gate configured to logically gate a plurality of first input data in response to the first clock signal, a second dynamic logic gate configured to logically gate a gating output of the first dynamic logic gate and a plurality of second input data, and a latching device configured to latch a gating output of the second dynamic logic gate. The digital logic circuit need not adopt a keeper circuit, and thus a gate delay is reduced and the digital logic circuit performs a high-speed gating operation with robust characteristic against a current leakage or an input noise.