Clockless RTS Domino Logic Gate With Self-Reset Evaluation
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Solution Overview
Problem
Conventional logic circuits require a clock signal for operation, which can be impractical in certain applications, especially when logic functions need to be performed at random locations on an integrated circuit, leading to inefficiencies and slower performance due to input capacitance and evaluation contention in static CMOS gates, and the reliance on clocked domino circuits.
Innovation Solution
A clockless return to state (RTS) domino logic gate is developed, comprising multiple nodes, a domino circuit, an evaluation circuit, an enable circuit, and a reset circuit, which switches between states without a clock, allowing for self-resetting operations based on input signals, enabling fast and efficient logic functions without a clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clocked domino circuits are used, then logic function speed is improved, but device complexity and clock routing requirements increase
Solution Approach 1:
The patent extracts and eliminates the clock signal requirement from the domino circuit operation. The clockless RTS domino circuit achieves timing and reset functionality through the inherent return-to-state behavior of RTS signals and local evaluation circuitry, removing the need for external clock distribution infrastructure.
Solution Approach 2:
The circuit uses self-resetting RTS signals that automatically return to their initial state after evaluation, enabling automatic reset of the domino circuit without external clock control. The evaluation circuit locally determines when resetting should occur based on input signal states, making the system self-regulating.
2Use of energy by moving object
If static CMOS gates are used, then power consumption is reduced, but input capacitance and evaluation contention increase causing slower performance
Solution Approach 1:
The patent employs dynamic domino circuit operation with precharge and evaluate phases controlled by RTS signals. The circuit transitions between states dynamically, allowing fast evaluation when needed while maintaining low power through the return-to-state mechanism that automatically resets the circuit for the next evaluation cycle.
Solution Approach 2:
The circuit operates in periodic cycles of evaluation and reset driven by RTS signal transitions. Each RTS signal assertion triggers an evaluation phase, followed by automatic reset when the signal returns to its initial state, creating a natural periodic operation rhythm that balances speed and power efficiency.
3Reliability
If clock signals are routed to logic circuits, then logic operation timing is controlled, but routing difficulty and impracticality increase at random locations
Solution Approach 1:
The RTS signal serves multiple functions simultaneously: it acts as the evaluation trigger, the clock equivalent for timing control, and the reset signal when it returns to its initial state. This multi-functionality eliminates the need for separate clock and reset signal routing infrastructure.
Solution Approach 2:
The evaluation circuit acts as an intermediary that locally interprets RTS signal states and controls domino circuit operation accordingly. This local evaluation mechanism eliminates the need for direct clock signal routing to each logic circuit, allowing placement at random locations without complex clock distribution.
Data Source
AI summary
A clockless return to state domino logic gate is disclosed responsive to multiple input nodes including at least one return to state node. A domino circuit presets a preset node to a second state. The domino circuit switches to a latch state and switches an output node when the preset node is pulled to a first state, and resets back to the preset state and switches the output node back to its default state when a reset node is pulled to the second state. An evaluation circuit pulls the preset node to the second state when the input nodes are in an evaluation state. An enable circuit enables a reset condition when the domino circuit is in its latch state. A reset circuit pulls the reset node to the first state after an evaluation event when the input nodes are no longer in the evaluation state.