Programmable Circuit Configuration Engine for Faster Frame Allocation
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Solution Overview
Problem
Conventional configuration engines for programmable integrated circuits, such as FPGAs, face inefficiencies and complexity in determining the number of frames for each circuit block type, leading to slow startup times and increased circuitry overhead due to the need for sequential frame and column counting with flag circuitry.
Innovation Solution
A configuration engine with a frame counter and row controller that uses a cascade of frame incrementer circuits to provide frame sums for each column, eliminating the need for flag circuitry by self-learning the configuration memory space and reducing complexity, allowing faster frame allocation and reduced circuitry overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional configuration engines use sequential frame and column counting with flag circuitry to determine the number of frames for each circuit block type, then the configuration process can be completed, but the startup time increases and circuit complexity increases due to the need for flag circuitry and sequential processing
Solution Approach 1:
The patent applies preliminary action by pre-organizing configuration memory cells into frames that are directly associated with specific circuit block types. The frame counter is pre-configured to count only the relevant frames for each circuit block type without requiring sequential column-by-column scanning. This preliminary organization allows the row controller to directly access and count frames for each circuit block type, eliminating the need for flag circuitry and reducing startup time.
Solution Approach 2:
The patent extracts and eliminates the flag circuitry from the configuration engine. Instead of using flag signals to indicate the end of frames or columns during sequential counting, the design directly counts frames associated with each circuit block type using a simplified frame counter. This extraction removes the harmful flag circuitry overhead while maintaining the ability to determine frame counts for each circuit block type efficiently.
2Productivity
If conventional configuration engines sequentially count frames and columns to determine configuration memory space, then all circuit blocks can be configured, but the startup time increases due to the sequential processing requirement
Solution Approach 1:
The patent applies preliminary action by pre-organizing configuration memory cells into frames that are directly associated with specific circuit block types before the configuration process begins. This pre-organization allows the row controller to directly access and count frames for each circuit block type without requiring sequential column-by-column scanning, significantly reducing startup time and configuration time.
Solution Approach 2:
The patent enables continuous useful action by allowing the frame counter to directly count frames for each circuit block type in parallel or sequential order without interruptions for flag signal generation or column scanning. The row controller can continuously access frame totals for different circuit block types, eliminating idle time associated with conventional sequential processing and flag circuitry operations.
Data Source
AI summary
Apparatus and method relate generally to a configuration engine. In one such configuration engine for a programmable circuit, a frame counter includes a cascade of frame incrementer circuits associated with columns for a row of circuit blocks. Each frame incrementer circuit is configured to provide frame sums for frames associated with the circuit blocks. The frame counter is configured to sequentially add the frame sums for the columns to provide corresponding frame totals respectively for circuit types of the circuit blocks. A termination circuit is configured to multiplex the frame totals onto a data bus. A row controller is configured to initiate the frame counter and to selectively access the frame totals provided to the data bus.