Crossover TFT Logic Circuit for Low-Power High-Speed Switching
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Solution Overview
Problem
Existing thin-film transistor circuits suffer from high power consumption due to their unipolar nature, lacking complementary devices, which limits their efficiency and battery life in mobile devices and RFID tags, and existing solutions like pseudo-CMOS and diode-load logic either consume too much power or compromise on speed and complexity.
Innovation Solution
A crossover logic circuit topology that combines the high-speed operation of diode load logic with the low power consumption of zero-VGS logic by using a specific configuration of thin-film transistors, including a first TFT connected to the input and output, a second TFT with a backgate for low leakage current, and a fourth TFT providing feedback for reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If diode load logic is used, then operational speed is improved, but power consumption increases
Solution Approach 1:
The circuit dynamically switches between diode load mode and zero-VGS mode based on the input signal state. When input is low, the load transistor operates in diode load mode (gate connected to drain) for high-speed operation. When input is high, the load transistor switches to zero-VGS mode (gate connected to source) for low-power operation, achieving adaptive optimization of both speed and power consumption.
Solution Approach 2:
The invention changes the operating parameters of the load transistor by switching its connection mode between diode load (gate-drain shorted) and zero-VGS (gate-source shorted) configurations. This parameter change allows the circuit to optimize between speed and power consumption based on operational requirements.
2Use of energy by moving object
If zero-VGS logic is used, then power consumption is reduced, but operational speed decreases
Solution Approach 1:
The circuit dynamically switches between zero-VGS mode and diode load mode based on input signal. When input is high, zero-VGS mode provides low power consumption. When input is low, diode load mode provides high operational speed. This dynamic switching resolves the speed-power tradeoff.
Solution Approach 2:
The circuit alternates between two operational modes (diode load and zero-VGS) depending on the input signal state, creating a periodic switching action that optimizes performance characteristics for different operational phases.
3Reliability
If pseudo-CMOS topology is used, then robustness and speed are improved, but power consumption increases and multiple supply voltages are required
Solution Approach 1:
The invention extracts and eliminates the bias network and multiple supply voltage requirements from the pseudo-CMOS topology. By using a simplified load transistor configuration that switches between diode load and zero-VGS modes, the circuit achieves robustness without requiring VBIAS or VSS connections, reducing power consumption and simplifying the power supply architecture.
Solution Approach 2:
The invention replaces the complex pseudo-CMOS structure with a simpler unipolar transistor-based circuit that uses standard thin-film transistor technologies. This substitution eliminates the need for complementary devices and multiple supply voltages, reducing manufacturing cost and power consumption while maintaining robustness.
4Area of stationary object
If dual-gate diode-load logic is used, then chip area is reduced, but power consumption remains large
Solution Approach 1:
The invention extends dual-gate transistor utilization to dynamically switch between diode load and zero-VGS modes. The backgate voltage is controlled to achieve mode switching, enabling the circuit to reduce power consumption while maintaining the compact area benefits of dual-gate transistor technology.
Solution Approach 2:
The invention changes the operational parameters of the dual-gate transistor by switching between diode load configuration (high speed) and zero-VGS configuration (low power). This parameter switching enables the circuit to achieve low power consumption while maintaining the area efficiency of dual-gate transistor implementation.
Data Source
Figure 1
Figure 2a~2b
AI summary
The invention relates to a logic circuit. The logic circuit comprises a first thin film transistor, TFT, having a gate connected to an input of the logic circuit, and a drain connected to an output of the logic circuit. The logic circuit further comprises a second TFT having a source connected to the output of the logic circuit. The logic circuit further comprises a third TFT having a gate connected to the input of the logic circuit, a source connected to the source of the second TFT, and a drain connected to a gate of the second TFT. The logic circuit further comprises a fourth TFT having a gate connected to the output of the logic circuit, and a source connected to the gate of the second TFT and the drain of the third TFT.