Dual-Trigger Flip-Flop Circuit With Low Clock Energy Load
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Solution Overview
Problem
Conventional digital flip-flop circuits consume significant power due to high clock-switched capacitance, and are sensitive to fabrication process variations, which affects their performance.
Innovation Solution
A dual-trigger, low-energy flip-flop circuit design that presents only three transistor gate loads to the clock signal, with internal nodes remaining static during stable states, and utilizing a low-frequency 'keeper clock' to reduce energy consumption and insensitivity to transistor sizing relationships.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional flip-flop circuits are used, then the circuit can store data, but the clock network consumes significant power due to high clock-switched capacitance
Solution Approach 1:
The flip-flop circuit is divided into two separate trigger circuits (first and second trigger circuits) that operate on different clock phases. This segmentation allows the clock signal to be switched only when necessary for data capture, reducing unnecessary clock switching and associated power consumption while maintaining reliable data storage functionality.
Solution Approach 2:
The circuit uses periodic clock signals with alternating phases (first clock signal and second clock signal) to control the two trigger circuits. This periodic action ensures that data is captured at appropriate intervals while keeping the clock network active only when needed, thereby reducing overall power consumption without compromising data storage reliability.
2Loss of energy
If the number of transistor gates coupled to the clock signal is reduced, then clock energy consumption decreases, but the circuit may become more sensitive to fabrication process variations
Solution Approach 1:
The circuit extracts and separates the clock switching function into dedicated clock-activated transistors in each trigger circuit. By isolating the clock switching operation to specific transistor gates (reducing the total number from 12 to fewer gates), the design reduces clock energy consumption while maintaining sufficient signal strength to be insensitive to fabrication variations through proper transistor sizing.
Solution Approach 2:
The circuit adjusts transistor sizing parameters (width-to-length ratios) to optimize the balance between reducing clock load and maintaining signal integrity. By carefully selecting transistor dimensions, the design achieves lower clock energy consumption while ensuring that the reduced number of transistor gates still provides adequate driving capability to overcome fabrication process variations.
3Productivity
If internal nodes are allowed to toggle during stable states, then the circuit can respond to data changes, but the number of toggling nodes increases energy consumption
Solution Approach 1:
The circuit implements dynamic control of internal nodes through the two-phase trigger mechanism. During stable states, internal nodes remain static to minimize energy consumption. When data changes occur, the appropriate trigger circuit is activated, allowing internal nodes to toggle dynamically only when necessary for data capture, thus balancing productivity with energy efficiency.
Solution Approach 2:
The circuit maintains continuous data storage capability through the cross-coupled latch structure while minimizing unnecessary toggling. The latch holds the data state continuously without requiring internal nodes to toggle during stable periods, ensuring productivity is maintained through continuous data retention while energy consumption is reduced by eliminating spurious transitions.
Data Source
AI summary
One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.