Bridged IC Architecture Using FPGA Decoding for Flexible ASIC Execution
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Solution Overview
Problem
The complexity in ASIC design leads to potential errors and increased development costs, and since ASICs are not reprogrammable, redesigns are necessary for different applications, which can delay product shipments and increase costs. Additionally, integrating multiple components in ASICs is beneficial for latency-critical applications but not for individual operations, where performance can be improved by offloading functionalities to a bridge chip.
Innovation Solution
A system comprising a Field-Programmable Gate Array (FPGA) and an Application-Specific Integrated Circuit (ASIC) on the same circuit board, where the FPGA decodes instructions and transmits them to the ASIC for execution, allowing the ASIC to be swapped for different applications and reducing design complexity by handling communications with external devices, thereby improving performance and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If ASIC design integrates multiple components for latency-critical applications, then performance is improved, but device complexity and development costs increase
Solution Approach 1:
The system divides functionality into two separate chips: an ASIC chip optimized for latency-critical computations and an FPGA chip handling control, instruction decoding, and external communications. This segmentation allows each chip to be specialized for its specific function, improving overall performance while reducing the complexity burden on any single component.
Solution Approach 2:
The FPGA chip acts as an intermediary between external devices and the ASIC chip. It handles instruction decoding, control logic, and communications, allowing the ASIC to focus purely on high-performance computations. This intermediary approach resolves the contradiction by offloading complex control functions from the ASIC.
2Speed
If ASIC is designed for a specific application, then performance is optimized, but adaptability for different applications decreases
Solution Approach 1:
The system combines a static ASIC optimized for specific computations with a dynamic FPGA that can be reprogrammed for different applications. The FPGA's reconfigurability provides adaptability, while the ASIC maintains optimized performance for its designated functions. This dynamic combination resolves the contradiction between specialization and flexibility.
Solution Approach 2:
The FPGA chip serves multiple functions: it decodes instructions, manages control logic, handles external communications, and can be reprogrammed for different applications. This multi-functionality provides the system with adaptability while the ASIC maintains its specialized high-performance capabilities.
3Adaptability or versatility
If ASIC redesign is performed for different applications, then adaptability is improved, but loss of time and productivity decrease
Solution Approach 1:
Instead of investing significant time and resources in redesigning expensive ASICs for different applications, the system uses a relatively inexpensive FPGA that can be reprogrammed quickly. The FPGA serves as a flexible, easily replaceable component that provides adaptability without the time cost of ASIC redesign cycles.
Solution Approach 2:
The system changes the programmable parameters of the FPGA to adapt to different applications, rather than changing the physical structure of an ASIC. This parameter-based adaptation (through reconfiguration and reprogramming) allows rapid transitions between applications without the time-consuming processes of mask fabrication and physical redesign associated with ASICs.
Data Source
AI summary
Methods, systems, and apparatus, including a system that includes a first integrated circuit chip configured to store application logic for one or more executable applications; and a second integrated circuit chip communicatively coupled to the first integrated circuit chip, the second integrated circuit chip including an instruction decoder configured to decode instructions for executing the one or more executable applications; and a communication interface configured to transmit the decoded instructions to the first integrated circuit chip to execute the one or more executable applications on the first integrated circuit chip.