Dual-Trigger Flip-Flop Circuit With Low Clock Energy Load
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Solution Overview
Problem
Conventional digital flip-flop circuits consume significant power due to high clock-switched capacitance, and are sensitive to fabrication process variations, which affects their performance.
Innovation Solution
A dual-trigger, low-energy flip-flop circuit design that presents only three transistor gate loads to the clock signal, with internal nodes remaining static during stable states, and utilizing a low-frequency 'keeper clock' to reduce energy consumption and insensitivity to transistor sizing relationships.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional flip-flop circuits use multiple transistor gates coupled to clock signals, then the clock signal can control the flip-flop operation, but the clock-switched capacitance increases leading to high power consumption
Solution Approach 1:
The patent extracts and eliminates redundant transistor gates from the clock path. Specifically, it removes unnecessary transistor gates that were previously coupled to clock signals, retaining only the essential three transistor gates (first, second, and third clock-activated transistor gates) that are required for proper flip-flop operation. This extraction of unnecessary components directly reduces clock-switched capacitance and power consumption while maintaining the required functionality.
Solution Approach 2:
The patent changes the operational parameters of the flip-flop by introducing a low-frequency keeper clock signal that toggles less frequently than the main clock signal. This parameter change in clock frequency allows the internal nodes to be updated less often, reducing the toggling activity and associated power consumption while maintaining data stability through the keeper function.
2Reliability
If conventional flip-flop circuits have internal nodes that toggle each clock cycle, then the flip-flop can update its state, but the clock load increases leading to higher energy consumption
Solution Approach 1:
The patent implements periodic action by using a low-frequency keeper clock signal that toggles at a lower frequency than the main clock signal. This periodic but reduced-frequency action allows internal nodes to be updated only when necessary for maintaining data stability, rather than toggling every clock cycle. The keeper clock provides periodic reinforcement of the stored state without requiring full clock-cycle updates of all internal nodes.
3Manufacturing precision
If conventional flip-flop circuits rely on transistor sizing relationships, then the circuit can be designed with specific performance characteristics, but the circuit becomes sensitive to fabrication process variations
Solution Approach 1:
The patent segments the flip-flop circuit into distinct functional blocks with clearly defined roles: trigger sub-circuit for state transition control, latch sub-circuit for data storage, and keeper sub-circuit for state maintenance. Each segment uses clock-activated transistors with standardized configurations. This segmentation allows each block to be optimized independently while maintaining overall robustness, reducing sensitivity to fabrication variations through modular design.
4Productivity
If the clock signal drives more transistor gates, then the clock can control more flip-flop elements, but the clock energy consumption increases
Solution Approach 1:
The patent extracts and removes redundant transistor gates from the clock distribution path, retaining only the three essential clock-activated transistor gates that are necessary for proper flip-flop operation. This extraction reduces the total clock load from potentially many transistor gates down to just three, directly reducing clock energy consumption while preserving the clock's ability to control the flip-flop state transitions effectively.
Data Source
AI summary
One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.