Programmable DSP Block Architecture With Hybrid FPGA Multipliers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional programmable semiconductor devices, such as FPGAs and PLDs, lack flexibility in their built-in digital signal processing (DSP) components, which limits their ability to perform various digital processing computations efficiently.
Innovation Solution
Incorporating a programmable digital signal processing block with hybrid multiplier blocks (HMBs) that include multipliers of different operand sizes, such as 27×18 and 12×12, allowing for configurable digital processing computations and enhanced flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dedicated custom integrated circuits or ASICs are used to implement desirable functions, then processing speed and efficiency are improved, but cost increases and flexibility is reduced
Solution Approach 1:
The patent implements DSP blocks within FPGAs that can be configured to perform multiple different digital signal processing functions. The DSP blocks contain programmable multipliers and accumulators that can be programmed via configuration memory to execute various algorithms, allowing a single hardware structure to serve multiple purposes - achieving both high processing speed (like ASIC) and flexibility (like FPGA).
Solution Approach 2:
The patent divides the FPGA into multiple independent DSP blocks, each capable of performing digital signal processing operations. These DSP blocks are segmented from the general logic blocks and can be independently configured and programmed. This segmentation allows parallel processing of multiple signal streams while maintaining the reconfigurability of the overall system.
2Productivity
If conventional FPGAs with built-in DSP components are used, then processing capabilities are provided, but flexibility is reduced
Solution Approach 1:
The patent implements dynamically reconfigurable DSP blocks where the multiplier dimensions (e.g., 18x18, 27x18, 36x18) can be changed at runtime through configuration memory programming. The control logic can dynamically adjust the operation mode of DSP blocks, allowing the same hardware to adapt to different algorithm requirements without physical reconfiguration, thus maintaining both processing capability and flexibility.
Solution Approach 2:
The patent allows changing operational parameters of the DSP blocks through configuration memory. The multiplier bit-widths, accumulation precision, and control signal parameters can be modified by loading different configuration data, enabling the same physical hardware to operate with different parameters suited for various digital signal processing applications.
Data Source
AI summary
A programmable logic device (“PLD”) contains programmable digital signal processing (“DSP”) blocks operable to be selectively programmed to perform one or more logic functions. The PLD, in one embodiment, includes configurable logic blocks (“LBs”), an input and output (“I/O”) block, and programmable DSP blocks. The configurable LBs are able to be selectively programmed to perform one or more logic functions. The I/O block includes I/O ports for facilitating data transfer. The programmable DSP blocks are configured to perform various predefined logic functions. Each of the programmable DSP blocks, in one aspect, includes at least one configurable DSP which, in one embodiment, includes a 27×18 multiplier and a 12×12 multiplier.