Dynamic CMOS Output Circuit for Low-Voltage Glitch Suppression
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Solution Overview
Problem
Dynamic semiconductor integrated circuits face challenges in achieving both speedup and malfunction protection during low-voltage operation, as the capability of PMOS transistors affects charge supply and potential changes at output nodes, leading to glitches and operational slowdowns.
Innovation Solution
The semiconductor integrated circuit design includes specific transistor configurations and feedback mechanisms, where PMOS and NMOS transistors are connected to manage charge supply and potential changes, ensuring glitch suppression and high-speed operation even at low voltages by controlling the conduction between power supplies and output nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the capability of the PMOS transistor is increased to prevent malfunctions during address miss, then malfunction protection is improved, but the charge cannot be drawn sufficiently when address hits during low-voltage operation, causing speedup to fail
Solution Approach 1:
The patent divides the single PMOS transistor function into two separate PMOS transistors: one dedicated to hold circuit protection (preventing glitches during address miss) and another dedicated to charge supply (enabling speedup during address hit). This segmentation allows each transistor to be optimized for its specific function without compromising the other, resolving the contradiction between reliability and speed.
Solution Approach 2:
The patent implements dynamic control of PMOS transistor capability through clock signal phases. During address hit conditions, the charge supply PMOS transistor is activated to provide strong drive capability for rapid charge drawing. During address miss conditions, the hold circuit PMOS transistor maintains protection capability. This dynamic switching allows the system to adapt transistor capability to operational requirements, simultaneously achieving both speedup and malfunction protection.
2Speed
If the capability of the PMOS transistor is reduced to enable charge drawing during low-voltage operation, then operation speed is improved, but glitches may grow and cause malfunctions during address miss
Solution Approach 1:
The patent segments the PMOS transistor functionality into two independent transistors with distinct roles. The charge supply PMOS transistor can be optimized for high drive capability to enable fast operation during address hit, while the hold circuit PMOS transistor is optimized for glitch prevention during address miss. This segmentation eliminates the need to compromise either function, allowing both speed and reliability to be maintained.
Solution Approach 2:
The patent introduces clock signal control as an intermediary mechanism that coordinates the operation of the two PMOS transistors. The clock signal phases ensure that the charge supply PMOS transistor operates during address hit conditions while the hold circuit PMOS transistor provides protection during address miss conditions. This intermediary control allows the system to achieve both fast operation and glitch prevention without direct conflict between the two functions.
3Device complexity
If a single PMOS transistor is used in the hold circuit, then device complexity is reduced, but it cannot simultaneously provide both malfunction protection and speedup during low-voltage operation
Solution Approach 1:
The patent divides the single PMOS transistor into two separate transistors with specialized functions. This segmentation increases component count but enables the circuit to handle multiple operational modes (address hit and address miss) effectively during low-voltage operation. The additional transistor provides the necessary versatility to maintain both protection and speedup capabilities that a single transistor cannot achieve.
Solution Approach 2:
The patent creates a multi-functional PMOS transistor system where two PMOS transistors work together to provide both hold circuit protection and charge supply functions. This universal approach allows the same type of transistor (PMOS) to fulfill multiple roles through proper configuration and clock control, achieving both malfunction protection and speedup capability within a unified circuit architecture.
Data Source
AI summary
The semiconductor integrated circuit includes: a first transistor of a first conductivity type connected between a first power supply and an output node and turned ON according to a first clock to put the output node to a first logic level; a second transistor of a second conductivity type turned ON according to an input signal; a third transistor of the second conductivity type connected in series to the second transistor and turned ON according to a second clock; and a fourth transistor of the first conductivity type connected between the first power supply and the output node and turned ON according to a feedback signal. The second and third transistors are connected between the output node and a second power supply. The fourth transistor is turned from ON to OFF after both the second and third transistors are turned ON.