FPGA Tile-to-Tile Interconnect Routing for Conflict and Congestion
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Solution Overview
Problem
Current FPGA routing techniques face challenges in efficiently and rapidly establishing desired interconnect architectures between logic tiles, particularly in handling conflicts and congestion within the tile-to-tile interconnect network, which affects communication efficiency and signal timing.
Innovation Solution
A routing technique that sequentially routes partial interconnect paths across subsets of non-contiguous logic tiles, allowing independent start/end points for each tile group, and includes re-routing steps to address conflicts and congestion, ensuring efficient and timely signal transmission through the tile-to-tile interconnect network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional routing techniques are used to establish tile-to-tile interconnects, then routing can be performed with simpler methods, but routing efficiency and speed are reduced due to conflicts and congestion
Solution Approach 1:
The routing process is divided into multiple passes, with each pass handling a specific subset of interconnects. The routing is segmented by interconnect type (horizontal, vertical, diagonal) and by direction (source-to-destination, destination-to-source), allowing conflicts to be resolved in an organized manner rather than all at once, thereby improving routing efficiency and reducing overall routing time
Solution Approach 2:
The routing algorithm performs preliminary actions by first identifying and reserving resources for critical interconnects before routing less critical ones. The method also performs preliminary conflict detection and resolution in early passes, preventing congestion from escalating and reducing the time needed for subsequent routing operations
2Reliability
If routing is performed for all logic tiles simultaneously, then complete interconnect paths can be established, but routing complexity and difficulty of managing conflicts increase
Solution Approach 1:
The set of all logic tiles is divided into groups that are routed in separate passes. Each pass handles a manageable subset of tiles and interconnects, reducing the complexity of conflict management in each individual pass while ensuring that all tiles are eventually connected through the complete multi-pass process
Solution Approach 2:
The routing algorithm dynamically adjusts the routing strategy based on the state of the interconnect network. Resources are reserved and released dynamically across passes, and the routing path selection adapts to previously established connections, allowing the system to manage complexity while maintaining complete interconnect paths
3Speed
If routing paths are optimized for speed, then signal transmission is faster, but routing conflicts and congestion increase
Solution Approach 1:
The algorithm performs preliminary resource reservation for high-speed interconnect paths before other routing operations. By securing resources for critical, speed-sensitive interconnects first, the system enables fast signal transmission while preventing conflicts from arising during subsequent routing of less time-critical interconnects
Solution Approach 2:
The routing method converts potential conflicts into benefits by using the routing process itself to identify and resolve congestion points. Conflicts that would normally slow down routing are instead used to inform resource allocation decisions, ensuring that high-speed paths are established through conflict-free routes while other interconnects adapt to available resources
Data Source
AI summary
A method of routing interconnects of a field programmable gate array including: a plurality of logic tiles, and a tile-to-tile interconnect network, having a plurality of tile-to-tile interconnects to interconnect logic tile networks of the logic tiles, the method comprises: routing a first plurality of tile-to-tile interconnects in a first plurality of logic tiles. After routing the first plurality of tile-to-tile interconnects, routing a second plurality of tile-to-tile interconnects in a second plurality of logic tiles. The start/end point of each tile-to-tile interconnect in the first plurality and the second plurality of tiles is independent of the start/end point of the other tile-to-tile interconnects in the first and second plurality, respectively. Routing the second plurality of tile-to-tile interconnects includes connecting at least one start/end point of each tile-to-tile interconnect in the second plurality of tiles to at least one start/end point of each interconnect in the first plurality of tiles.