Null Convention Logic Gates Without External Clock Synchronization
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Solution Overview
Problem
Traditional digital logic circuits require external clocks to determine completion of logic operations, leading to increased power consumption and complexity, especially in mobile devices, due to the need for wide distribution of clock signals and synchronization.
Innovation Solution
Implementing null convention logic (NCL) circuits that use two signal lines to represent binary values and a null state, allowing data elements to self-indicate validity without a centralized clock, reducing the need for external synchronization and enabling compact logic evaluation gates with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional digital logic circuits use external clocks for synchronization, then logic operation completion can be determined, but power consumption and circuit complexity increase due to wide distribution of clock signals
Solution Approach 1:
The patent extracts the clock signal distribution system from the logic circuit architecture. By using NCL's inherent validity signaling mechanism, the external clock infrastructure is removed entirely, eliminating the power consumption associated with generating and distributing clock signals across the circuit board.
Solution Approach 2:
The NCL circuit performs self-synchronization by using the validity signal inherently present in its data representation. The circuit determines completion of logic operations through its own internal state (validity signaling) rather than relying on external clock commands, making the system self-sufficient and eliminating external synchronization overhead.
2Ease of operation
If traditional digital logic circuits use external clocks for synchronization, then logic operation timing can be controlled, but device complexity increases due to synchronization requirements
Solution Approach 1:
The patent removes the external clock distribution network and synchronization control logic from the system. The NCL architecture inherently encodes timing and validity information in its data representation, eliminating the need for separate clocking infrastructure and reducing overall device complexity.
Solution Approach 2:
The validity signal in NCL serves multiple functions simultaneously: it indicates data readiness, signals completion of logic operations, and enables downstream circuit activation. This multi-functionality replaces what would traditionally require separate clock and control signals, simplifying the overall control architecture.
3Use of energy by stationary object
If NCL circuits use validity signaling without external clocks, then power consumption is reduced, but data validity detection complexity increases
Solution Approach 1:
The patent merges the data value and validity information into a unified NCL signal representation. Rather than requiring separate detection circuits for validity, the validity state is encoded directly in the signal levels themselves, allowing standard NCL logic gates to detect and process validity information as part of their normal operation.
Data Source
AI summary
Compact logic evaluation gates are built using null convention logic (NCL) circuits. The inputs to a null convention circuit include a NCL true input and a NCL complement input. The NCL circuit includes a gate coupled to the pair of inputs, where the gate comprises a plurality of transistors. The transistors allow for logical signal capture, provide a pair of cross-coupled inverters for data storage, and include a first and second pull-down device. The first pull-down device causes a first side of the pair of cross-coupled inverters to go to a “0” state when a “1” is applied to the NCL true input, and the second pull-down device causes a second side of the pair of cross-coupled inverters to go to a “0” state when a “1” is applied to the NCL complement input.