Compact Arithmetic Elements for More Operations Per Transistor
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Solution Overview
Problem
Conventional computing systems waste transistors by using high precision arithmetic operations, limiting the ability to harness the full computing power of silicon chips, as they are designed to maintain software compatibility and precision rather than optimizing performance per transistor.
Innovation Solution
Implementing low precision high dynamic range (LPHDR) processing elements that perform arithmetic operations with a precision of about 0.1%, allowing for a greater number of operations per unit of time and power, and using logarithmic or analog representations to reduce circuit area and increase parallel processing capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high precision arithmetic operations are used, then software compatibility and precision are maintained, but the number of operations per transistor is limited
Solution Approach 1:
The patent changes the precision parameter from traditional high precision (32-bit or 64-bit floating point) to low precision (8-bit or 16-bit integer arithmetic). This parameter change allows dramatically more operations to be performed per transistor while maintaining sufficient accuracy for many computational tasks through techniques like Kahan summation and randomized rounding
Solution Approach 2:
The patent segments the arithmetic operations into multiple lower-precision steps rather than performing single high-precision operations. By breaking down computations into sequences of simpler operations with intermediate rounding and correction steps, the system achieves both high throughput and acceptable precision
2Power
If more arithmetic elements are implemented, then computing power increases, but chip area increases
Solution Approach 1:
The patent uses inexpensive, simple arithmetic elements that can be densely packed on the chip. Each processing element uses basic integer arithmetic units rather than complex floating-point units, allowing hundreds or thousands of elements to fit on a single chip. These simple elements are replicated many times to achieve massive parallelism
Solution Approach 2:
By changing from high-precision floating-point arithmetic to low-precision integer arithmetic, the patent reduces the area required for each arithmetic element by an order of magnitude or more, enabling dense arrays of processing elements that provide high computing power in a compact footprint
3Measurement precision
If traditional floating point arithmetic is used, then precision is maintained, but dynamic range is limited
Solution Approach 1:
The patent implements dynamic range extension through runtime scaling and exponent tracking. Each low-precision value is accompanied by scale factors or exponent information that allows the system to represent both very small and very large numbers. The arithmetic operations dynamically adjust scaling to maintain precision across a wide dynamic range, enabling representation from 1e-308 to 1e+308 equivalent ranges
Data Source
AI summary
A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).