FPGA Switch Box Checkerboard Layout for Lower Chip Area
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Solution Overview
Problem
The existing architecture of integrated circuits with programmable logic, such as FPGAs, incurs excessive resource expenditure on connection elements, leading to inefficient use of chip area and routeability.
Innovation Solution
Implementing a grid-based structure where configurable logic blocks are arranged without switch boxes at every coordinate, using a chessboard pattern with alternating switch boxes connected parallel to coordinate axes and diagonally, and employing two types of switch boxes to reduce the number of switch boxes while maintaining routeability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a switchbox is assigned to every Configurable Logic Block (CLB) in the island-style topology, then good routeability and signal path configurability are achieved, but the chip area and circuit complexity are significantly increased
Solution Approach 1:
Multiple CLBs share common switchboxes located at grid coordinate intersections rather than each CLB having its own dedicated switchbox. This merging approach reduces the total number of switchboxes while maintaining routing capability through the shared infrastructure.
Solution Approach 2:
Switchboxes are designed to serve multiple CLBs simultaneously, acting as universal routing nodes that can handle signals from any direction. Each switchbox can configure signal paths for multiple adjacent CLBs, reducing overall circuit complexity while maintaining adaptability.
2Adaptability or versatility
If switchboxes are placed at every grid coordinate intersection, then comprehensive signal routing in all directions is enabled, but the number of connecting elements and circuit complexity increase significantly
Solution Approach 1:
The routing function is segmented between CLBs and shared switchboxes. CLBs generate and consume signals, while switchboxes handle direction changes and path configuration. This segmentation allows complex routing functionality to be distributed efficiently rather than concentrated in every CLB.
Solution Approach 2:
Switchboxes are placed only at necessary grid coordinate intersections rather than at every possible location. This partial placement provides sufficient routing capability for typical signal paths while avoiding the excessive complexity that would result from universal placement.
3Area of stationary object
If the number of switchboxes is reduced to half the number of CLBs, then chip area is significantly reduced, but routing capability must be maintained through strategic placement
Solution Approach 1:
Switchboxes are strategically placed at specific grid coordinate intersections where they provide maximum routing value. The placement optimizes local routing density and signal path efficiency, ensuring that reduced numbers of switchboxes still provide comprehensive coverage.
Solution Approach 2:
The patent uses a two-dimensional grid coordinate system to organize and place switchboxes efficiently. By thinking in terms of grid coordinates and intersections, the placement optimizes spatial utilization and ensures comprehensive routing coverage with minimal switchbox density.
Data Source
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AI summary
Switchboxes are used particularly in integrated circuits with programmable logic (e.g., FPGAs). They serve to establish configurable signal paths between logic blocks. It is especially important to use an efficient structure, i.e., a structure with the smallest possible chip area and capable of implementing short and fast signal paths. The object of the present invention is to significantly reduce the complexity of the interconnect structures while still maintaining good routable routing. This is achieved by having a logic block (CLB) at each coordinate position, but not by placing a switchbox (SB) at every coordinate position. It is particularly advantageous to arrange the SBs in a checkerboard pattern and to use two SBs of different sizes arranged in a higher-level checkerboard structure.