Programmable Logic DSP Block Routing for Low-Latency Cascading
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Solution Overview
Problem
Existing digital signal processing (DSP) block designs in programmable logic devices (PLDs) lack flexibility in signal routing and synchronization, leading to significant latencies and complications when performing operations that require multiple DSP blocks, as they often do not provide convenient ways to route signals between rows of DSP blocks.
Innovation Solution
The implementation of a dedicated DSP block with two multipliers and a ternary arithmetic logic unit (ALU) that allows for cascading of signals between DSP slices, selective latching by register blocks to reduce latency, support for single instruction multiple data (SIMD) operations, flexible routing of output signals to other DSP blocks, and memory-saving rounding operations, along with programmable sign extension capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If DSP blocks are arranged in a finite number of rows with limited routing options, then device complexity is reduced, but adaptability and ease of operation deteriorate when routing signals between rows
Solution Approach 1:
The DSP block is designed with universal input and output interfaces that can handle both intra-row and inter-row signal routing through the same physical structures. The carry-in and carry-out signals are configured to accept and provide both product signals from adjacent DSP blocks in the same row and sum signals from DSP blocks in other rows, eliminating the need for separate routing paths and enhancing adaptability without increasing device complexity.
2Reliability
If intermediate results are latched between multiple pipelined DSP blocks, then processing reliability is improved, but processing speed deteriorates due to significant latencies
Solution Approach 1:
The design enables continuous data flow through DSP blocks by allowing carry-out signals to directly provide product signals to the next DSP block without mandatory latching at each stage. The arithmetic logic unit can continuously generate sum signals that are carried to other rows, maintaining an uninterrupted processing stream that preserves reliability while minimizing latency and maximizing processing speed.
Data Source
AI summary
Various implementations of a digital signal processing (DSP) block architecture of a programmable logic device (PLD) and related methods are provided. In one example, a PLD includes a dedicated DSP block. The DSP block includes a first multiplier adapted to multiply a first plurality of input signals to provide a first plurality of product signals. The DSP block also includes a second multiplier adapted to multiply a second plurality of input signals to provide a second plurality of product signals. The DSP block further includes an arithmetic logic unit (ALU) adapted to operate on the first product signals and the second product signals received at first and second operand inputs, respectively, of the ALU to provide a plurality of output signals.