Configurable Arithmetic Block for Word-Oriented DSP Logic
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Solution Overview
Problem
Conventional programmable logic devices (PLDs) are inefficient in implementing arithmetic functions for digital signal processing (DSP) applications, with high costs, power consumption, and low density due to inefficient bit-oriented interconnect patterns, lack of support for arbitrary word sizes, and inefficient hardware resource allocation.
Innovation Solution
A configurable arithmetic block in a programmable logic device that includes input registers, an arithmetic function circuit, an output selection circuit, and output registers, enabling carry functions and sharing of arithmetic circuits between blocks, optimized for DSP operations with support for various word sizes and improved pipeline balancing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional bit-oriented interconnect patterns are used in PLDs, then device complexity is reduced, but arithmetic operation density and performance deteriorate
Solution Approach 1:
The patent changes the fundamental parameter of interconnect organization from bit-oriented to word-oriented. Word-oriented interconnects transfer multiple bits simultaneously as complete words, dramatically increasing arithmetic operation density while the regular structure actually simplifies the interconnect control logic compared to complex bit-level routing
2Adaptability or versatility
If conventional PLD architectures are used, then ease of manufacture is maintained, but support for arbitrary word sizes deteriorates
Solution Approach 1:
The patent creates a universal word-oriented arithmetic block that can handle arbitrary word sizes through configurable parameters. The same hardware structure adapts to different word lengths (16-bit, 32-bit, etc.) by configuring the number of parallel bit-slices, eliminating the need for multiple specialized architectures while maintaining manufacturing simplicity
3Adaptability or versatility
If heterogeneous blocks are used for multipliers and DSP functions, then adaptability is improved, but device complexity and optimization difficulty increase
Solution Approach 1:
The patent merges previously separate heterogeneous blocks (multipliers, adders, DSP functions) into a unified word-oriented arithmetic block. This single configurable structure can perform multiplication, addition, subtraction, and other DSP operations by configuring the arithmetic function circuit, reducing device complexity while maintaining full DSP functionality
4Productivity
If conventional PLDs are used, then ease of operation is maintained, but resource utilization efficiency deteriorates
Solution Approach 1:
The patent introduces dynamic configurability where the arithmetic block can be programmed at compile time to optimize for specific operations. The configuration data bits stored in memory cells allow the hardware to be dynamically reconfigured for different DSP algorithms, maximizing resource utilization while the configuration process remains abstract and easy to use through high-level synthesis tools
Data Source
AI summary
A configurable arithmetic block in a device having programmable logic for implementing arithmetic functions is disclosed. The configurable arithmetic block comprises a plurality of input registers coupled to receive multiple bit words; an arithmetic function circuit coupled to receive the multiple bit words; an output selection circuit coupled to receive the output of the plurality of input registers and an output of the arithmetic function circuit; and a plurality of output registers coupled the output selection circuit. A method of implementing arithmetic functions in a device having programmable logic is also disclosed.