Crossover TFT Logic Circuit for Low-Power Unipolar Operation
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Solution Overview
Problem
Thin-film transistor circuits face high power consumption due to the unipolar nature of some technologies, lacking complementary devices, which limits their efficiency and battery life in mobile devices and RFID tags, and existing solutions like pseudo-CMOS and dynamic logic either increase complexity or require multiple supply voltages.
Innovation Solution
A crossover logic circuit topology that combines the high-speed performance of diode load logic with the low power consumption of zero-VGS logic, using a specific configuration of thin film transistors with controlled threshold voltages and backgates to reduce power consumption and eliminate multiple current branches between supply rails.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pseudo-CMOS topology is used to improve robustness and speed, then operational performance is improved, but power consumption remains high and circuit complexity increases
Solution Approach 1:
The patent changes the operating parameters of the load transistor by using zero-VGS operation (gate-source voltage of zero) instead of the conventional on-state operation. This parameter change reduces the power consumption significantly while maintaining the robustness and speed improvements through the complementary transistor configuration.
2Device complexity
If diode-load logic is used to simplify circuit structure, then device complexity is reduced, but power consumption remains large due to on-state load transistor
Solution Approach 1:
The patent modifies the operating parameter of the load transistor from on-state (VGS > 0) to zero-VGS state, which dramatically reduces power consumption while keeping the circuit structure relatively simple. The complementary transistor is added to enable this parameter change without requiring complex circuit reconfiguration.
3Adaptability or versatility
If multiple current branches are used between VDD and ground, then circuit functionality is enhanced, but power consumption increases
Solution Approach 1:
The patent extracts or removes the unnecessary current branches between VDD and ground by using the zero-VGS load transistor configuration. This eliminates multiple parallel current paths that would otherwise consume power, while retaining the essential circuit functionality through the complementary transistor arrangement.
Data Source
AI summary
The disclosure relates to a logic circuit. The logic circuit comprises a first thin film transistor, TFT, having a gate connected to an input of the logic circuit, and a drain connected to an output of the logic circuit. The logic circuit further comprises a second TFT having a source connected to the output of the logic circuit. The logic circuit further comprises a third TFT having a gate connected to the input of the logic circuit, a source connected to the source of the second TFT, and a drain connected to a gate of the second TFT. The logic circuit further comprises a fourth TFT having a gate connected to the output of the logic circuit, and a source connected to the gate of the second TFT and the drain of the third TFT.