Network FPGA Programming via Frame Parsing Logic
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Solution Overview
Problem
Existing methods for programming Field Programmable Gate Arrays (FPGAs) face challenges with slow and disruptive indirect updates via JTAG, speed limitations due to direct non-volatile memory updates, manageability issues, and increased complexity and costs associated with using auxiliary processors for network booting.
Innovation Solution
A method for programming FPGAs via a network using a predetermined communications protocol, employing a permanently programmed logic component to establish a communications connection, parse frames, and write programming data directly to the FPGA, with minimal external devices and logic, enabling self-booting from the network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If indirect update via JTAG is used, then the FPGA can be programmed, but the process is very slow and disruptive since the FPGA features are not available during update
Solution Approach 1:
The patent introduces an intermediary boot processor that mediates between the network and the FPGA. This boot processor handles the initial boot sequence and FPGA configuration, allowing the FPGA to be programmed without disrupting its operational features. The boot processor acts as a mediator that enables simultaneous FPGA operation and configuration updates.
2Productivity
If direct update via FPGA is used, then the update is faster and less disruptive, but the speed is limited by the non-volatile memory and requires dual boot images
Solution Approach 1:
The boot processor serves as an intermediary that decouples the FPGA from direct dependency on non-volatile memory for booting. The boot processor loads the FPGA configuration image from the non-volatile memory and transfers it to the FPGA, enabling faster updates without requiring the FPGA to directly manage dual boot images or complex memory structures.
Solution Approach 2:
The system uses a copying mechanism where the boot processor copies the FPGA configuration image from the non-volatile memory to the FPGA's volatile memory or direct logic. This copying approach eliminates the need for the FPGA to directly manage complex dual-boot image structures in the non-volatile memory, simplifying the memory structure while maintaining update speed.
3Adaptability or versatility
If an auxiliary processor is added for network booting, then the FPGA can boot from network, but the board space, complexity and costs increase
Solution Approach 1:
The boot processor is designed with multi-functionality, serving as both the network interface controller and the FPGA configuration loader. This universal component handles multiple tasks including network communication, image validation, and FPGA programming initiation, thereby providing network booting capability without requiring multiple separate auxiliary components, thus reducing board space and overall system complexity.
4Device complexity
If low-cost microprocessors are used for network booting, then costs are reduced, but they are not fast enough to support modern network speeds
Solution Approach 1:
The system employs a copying strategy where the boot processor copies only the essential FPGA configuration image data from the network to the FPGA, rather than processing entire network protocols or large data sets. This selective copying approach minimizes the computational burden on the low-cost microprocessor, enabling it to support modern network speeds without requiring high-performance or expensive processors.
Data Source
AI summary
A method for programming a Field Programmable Gate Array (FPGA) via a network, the network being operated according to a predetermined communications protocol, can include: establishing a communication connection between the FPGA and an external master, setting the FPGA into a programming mode, the master providing an FPGA programming image to the FPGA in a sequence of frames so that the frames can be parsed and enabling the FPGA to write only during receiving the payload section of the frames. The FPGA programming image and parsing the sequence of frames can be performed by a permanently programmed or hardwired logic component. A network, FPGA, and a communication system can be configured to utilize embodiments of the method.